Flash Memory Data Retention Bias for Charge Leakage
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Solution Overview
Problem
NAND flash memory arrays face significant data retention issues as memory cell sizes decrease, leading to shorter data retention times and increased probability of electron leakage, which can result in misreading of memory states, especially in smaller devices where even a few lost electrons can cause significant threshold voltage shifts.
Innovation Solution
Applying a data retention bias to one or more word lines when the memory die is idle, using a word line bias generator to maintain a suitable voltage that reduces the probability of electron leakage through the gate dielectric, while avoiding excessive voltage that could cause electrons to leak up to the control gate, and selectively applying this bias based on temperature, wear-count, and other factors to optimize power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell dimensions are reduced to increase storage capacity, then storage density is improved, but data retention time deteriorates due to increased electron leakage probability
Solution Approach 1:
The patent applies a preliminary counteracting voltage (data retention bias) to the control gate before data loss occurs. This bias voltage creates an electrostatic field that opposes and prevents electron leakage from the floating gate during idle periods, thereby compensating for the increased leakage tendency in scaled-down cells while maintaining high storage density
Solution Approach 2:
The patent dynamically changes the voltage parameter of the control gate by applying a data retention bias during idle periods. This parameter change (voltage application) modifies the electrostatic conditions to prevent charge loss, allowing small memory cells to maintain data retention comparable to larger cells without sacrificing storage capacity
2Reliability
If a data retention bias is applied to word lines during idle periods, then data retention is improved, but power consumption increases
Solution Approach 1:
The patent applies data retention bias periodically or selectively during idle periods rather than continuously. The bias is applied when the memory device is idle and not executing commands, and can be selectively applied based on temperature conditions, wear-count, or other factors, thereby reducing overall power consumption while maintaining data retention during critical periods
Solution Approach 2:
The data retention bias is applied in advance during idle periods before data corruption can occur. By proactively maintaining the electrostatic field during non-operational times, the patent prevents data loss without requiring continuous power consumption during active operations
3Reliability
If excessive voltage is applied to word lines to prevent electron leakage, then data retention is improved, but electrons may leak upward to the control gate causing data corruption
Solution Approach 1:
The patent carefully controls the voltage parameter of the data retention bias to fall within an optimal range. The bias voltage is sufficient to prevent downward electron leakage from floating gates but remains below the threshold that would cause upward electron migration to control gates, thereby solving the contradiction through precise parameter optimization
Solution Approach 2:
The control gate voltage acts as an intermediary that mediates between preventing electron leakage from floating gates and avoiding electron injection into the control gate. By carefully selecting the bias voltage level, the system finds an intermediate value that provides protection without causing harmful side effects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The data retention bias effectively reduces the likelihood of charge loss in floating gates, improving data retention times and maintaining accurate memory states by creating an electrostatic force that counteracts electron leakage, even during extended idle periods, thereby enhancing the reliability of flash memory arrays.
Implementation Method 1
The data retention bias effectively reduces the likelihood of charge loss in floating gates, improving data retention times and maintaining accurate memory states by creating an electrostatic force that counteracts electron leakage
Implementation Method 2
Applying a data retention bias to one or more word lines when the memory die is idle, using a word line bias generator to maintain a suitable voltage that reduces the probability of electron leakage through the gate dielectric
Data Source
AI summary
Charge leakage from a floating gate in a NAND flash memory die is reduced by applying a data retention bias to a word line extending over the floating gates. The data retention bias is applied to one or more selected word lines when the memory die is in idle mode, when no read, write, erase, or other commands are being executed in the memory die.