3D Flash Memory Channel Ring Structure for Leakage Control
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Solution Overview
Problem
Current 3D memory devices face challenges in reducing leakage current and improving turn-on current ratio due to insufficient control over the channel region, which affects the performance and efficiency of memory cells.
Innovation Solution
The implementation of a memory device with doped channel rings separated by insulating layers, which are alternately stacked with gate layers to enhance control over the channel region, reduce leakage current, and increase the device window, while allowing for modulation of the threshold voltage by adjusting dopant concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If channel rings are physically separated by insulating layers, then leakage current is reduced and device window is increased, but manufacturing complexity increases
Solution Approach 1:
The channel region is segmented into multiple discrete channel rings separated by insulating layers. This segmentation physically isolates adjacent channel regions, preventing leakage current paths between them and improving device reliability without requiring complex external control mechanisms
Solution Approach 2:
The insulating layers are formed between channel rings during the fabrication process before final device operation. This preliminary structuring establishes the leakage prevention architecture early in manufacturing, simplifying the overall process by integrating the solution into the fabrication sequence rather than requiring post-processing modifications
2Productivity
If dopant concentration in channel rings is increased, then turn-on current is improved, but threshold voltage control becomes more difficult
Solution Approach 1:
Different dopant concentrations are applied to different channel rings based on their specific functional requirements. This local quality approach allows optimization of turn-on current in specific rings while maintaining appropriate threshold voltage control in others, resolving the contradiction between current enhancement and precision control
Solution Approach 2:
The dopant concentration parameter is varied across different channel rings to achieve desired electrical characteristics. By changing this parameter locally rather than uniformly, the invention optimizes both turn-on current and threshold voltage control for different device regions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces leakage current, enhances the turn-on current ratio, and improves the operational speed and efficiency of memory cells by better controlling the channel region and modulating the threshold voltage.
Implementation Method 1
A doping process is performed on the plurality of channel rings to form a plurality of doped channel rings
Data Source
AI summary
A memory device may be applicated in a 3D AND flash memory device. The memory device includes a gate stack structure, a doped channel stack structure, a source pillar and a drain pillar, and a plurality of dielectric structures. The gate stack structure is located on a substrate. The gate stack structure includes a plurality of gate layers and a plurality of insulating layers stacked alternately with each other. The doped channel stack structure extends through the gate stack structure. The doped channel stack structure includes a plurality of doped channel rings spaced apart from each other. The source pillar and the drain pillar extend through the doped channel stack structure. The source pillar and the drain pillar are respectively electrically connected to the plurality of doped channel rings. The plurality of dielectric structures are located between the plurality of gate layers and the plurality of doped channel rings.