Flash Memory Control Unit RAM Instruction Buffering
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Solution Overview
Problem
Conventional flash memory devices require a lengthy consecutive time period to execute data access commands, hindering optimization and flexibility in scheduling multiple commands due to the need for continuous register writing.
Innovation Solution
A method and device that allow the control unit to read interface-driving instructions from RAM instead of continuously writing them into registers, enabling the storage-unit access interface to operate based on these instructions, thereby reducing the necessary consecutive time period for register writing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If firmware continuously writes registers to execute data access commands, then the storage-unit access interface can be operated correctly, but the consecutive time period required is lengthy and flexibility is reduced
Solution Approach 1:
The patent applies preliminary action by pre-loading interface-driving instructions into a buffer memory before execution. Instead of writing registers sequentially during command execution, the firmware prepares the complete sequence of control signals, addresses, and parameters in advance in the buffer memory. This allows the control unit to fetch and execute multiple commands from the buffer without requiring continuous firmware intervention, thereby reducing the consecutive time period needed while ensuring reliable operation.
2Reliability
If firmware continuously writes registers for data access commands, then control signals can be asserted and de-asserted properly, but scheduling optimization for multiple commands is hindered
Solution Approach 1:
The patent applies segmentation by dividing the command execution process into separate functional components. Interface-driving instructions are segmented into discrete units stored in buffer memory, each representing a specific control signal assertion or de-assertion. This segmentation allows the firmware to schedule and load multiple command sequences independently into the buffer, providing flexibility in optimizing the scheduling of multiple data access commands while ensuring each control signal is properly managed.
3Reliability
If five to twenty registers are written consecutively without interruption, then data access commands can be executed, but the process cannot be interrupted and efficiency is limited
Solution Approach 1:
The patent introduces an intermediary buffer memory between the firmware and the register writing process. Instead of the firmware directly writing 5-20 registers in an uninterruptible sequence, the interface-driving instructions are first transferred to the buffer memory as an intermediary storage. The control unit then retrieves instructions from this buffer, allowing the process to be interrupted and rescheduled. This intermediary mechanism maintains reliable command execution while significantly improving data access efficiency through flexible scheduling.
Data Source
AI summary
An embodiment of a method for executing data access commands, performed by a control unit, is disclosed to include at least the following steps. A series of interface-driving instructions is read from a RAM (Random Access Memory) after detecting that an indication for altering instruction source has been written into a register. A storage-unit access interface is operated according to the interface-driving instructions, so as to complete data access to a storage unit.