Flash Memory Controller Error Correction for Bad Block Reduction
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Solution Overview
Problem
Flash memory devices face reliability issues due to increased error rates and bit flips after repeated program/erase cycles, leading to uncorrectable data errors and potential bad blocks, which complicates data retention and system performance.
Innovation Solution
A memory controller system that includes an error detection and correction circuit, processing unit, and memory interface to detect error bits, determine correctability, and generate representative values for uncorrectable sectors, allowing for error correction and reducing the occurrence of bad blocks by re-reading data multiple times and analyzing sector consistency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If flash memory devices are programmed or erased multiple times to increase storage capacity and usage flexibility, then adaptability and versatility improve, but reliability deteriorates due to increased error rates and bit flips
Solution Approach 1:
The system performs preliminary error detection and correction by reading data multiple times before final storage. By anticipating potential errors from repeated program/erase cycles and correcting them proactively, the system maintains data reliability while allowing flexible usage patterns.
Solution Approach 2:
The error detection and correction circuit continuously monitors data integrity and provides feedback to the control logic. When errors are detected in repeatedly accessed data, the system triggers re-reading and correction processes, creating a closed-loop feedback mechanism that maintains reliability despite multiple program/erase cycles.
2Reliability
If error detection and correction circuits are added to detect and correct data errors, then reliability improves, but device complexity increases
Solution Approach 1:
The error detection and correction system uses the existing memory structure and data paths to perform self-diagnosis and self-correction. The control logic leverages the memory's own read capabilities to re-read problematic data and generate correction values, eliminating the need for separate complex correction hardware.
Solution Approach 2:
The control logic performs multiple functions: it manages normal read/write operations, detects errors, initiates re-reading sequences, generates correction values, and updates stored data. This multi-functional approach consolidates error correction capabilities within the existing control structure rather than adding dedicated correction hardware.
3Reliability
If data is re-read multiple times to correct errors and reduce bad blocks, then reliability improves, but productivity decreases due to increased access time
Solution Approach 1:
The system performs error correction selectively rather than for all data accesses. Error detection and re-reading are triggered only when errors are actually detected, not on every read operation. This partial application of the correction process minimizes the impact on overall productivity while maintaining reliability for problematic data.
Solution Approach 2:
The system takes preliminary corrective action by detecting and fixing errors during the first read operation when possible. By identifying and correcting errors early in the access sequence rather than requiring multiple full read cycles, the system reduces the overall time penalty while maintaining data reliability.
Data Source
AI summary
A nonvolatile memory device includes a nonvolatile memory, a buffer memory configured to store a plurality of read data transmitted from the nonvolatile memory, an error detection and correction circuit configured to detect an error in partial data of each of the plurality of read data and judging whether the partial data is correctable or not on the basis of the detected error, and a controller configured to analyze the uncorrectable partial data with respect to the plurality of read data to determine a representative value, and to transmit the representative value to the error detection and correction circuit. The plurality of read data is read through a read operation with respect to a same page.