Flash Memory Program-Verify Voltage Offset Adjustment for CSL Noise
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Solution Overview
Problem
Common source line (CSL) noise in flash memory devices leads to increased threshold voltage distribution widths, causing errors in read and program-verify operations by incorrectly determining on-cells as off-cells due to voltage increases during these operations.
Innovation Solution
A method and device that perform a two-stage program-verify operation by selecting one of two verify voltages based on the noise level of the common source line, using a control logic circuit to adjust the offset between these voltages to accurately determine the program state of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current flows in on-cell during read or program-verify operation, then the cell operates normally, but CSL noise increases causing voltage increase and current decrease leading to wrong determination
Solution Approach 1:
The patent applies preliminary anti-action by pre-compensating for CSL noise effects before the actual read or program-verify operation. The control circuit predicts the noise level based on program operation history and adjusts verify voltages in advance to counteract the expected voltage increase, preventing wrong cell state determination before it occurs
Solution Approach 2:
The patent changes verify voltage parameters dynamically based on noise conditions. The control circuit selects different verify voltages from multiple available voltages depending on the predicted CSL noise level, adjusting the voltage parameter to maintain adequate margin between the verify voltage and the noise-induced voltage shift
2Measurement precision
If verify voltage is increased to account for CSL noise, then on-cell detection accuracy improves, but off-cell detection may be affected and device complexity increases
Solution Approach 1:
The patent implements dynamics by making the verify voltage selection adaptive and dynamic rather than static. The control circuit dynamically adjusts which verify voltage to use based on real-time assessment of program operation history and predicted noise levels, allowing the system to optimize detection accuracy for each specific operation context
Solution Approach 2:
The patent segments the verify voltage selection into discrete levels or categories. Instead of continuously adjusting voltage, the control circuit selects from a finite set of verify voltages, each optimized for different noise conditions. This segmentation simplifies the control logic while maintaining measurement precision
3Reliability
If multiple verify voltages are used to handle different noise levels, then detection accuracy under varying noise conditions improves, but operation time and complexity increase
Solution Approach 1:
The patent performs preliminary action by predicting the appropriate verify voltage before the actual verification operation. The control circuit analyzes program operation history and noise patterns in advance to pre-select the optimal verify voltage, eliminating the need for iterative voltage adjustments during the verification process itself
Solution Approach 2:
The patent applies partial action by using a limited subset of available verify voltages only when necessary based on predicted noise levels. For low-noise conditions, the system uses a standard verify voltage, while only switching to alternative voltages when noise prediction exceeds thresholds, avoiding unnecessary complexity
Data Source
AI summary
A nonvolatile memory device and a method of operating the same are provided. The method includes performing a plurality of program operations on a plurality of memory cells each to be programmed to one of a plurality of program states, performing a program-verify operation on programmed memory cells associated with each of the plurality of program states, the program-verify operation comprises, selecting one of the plurality of offsets based on a noise level of a common source line associated with a programmed memory cell, using the selected offset to select one of a first verify voltage and a second verify voltage higher than the first verify voltage, and verifying a program state of the programmed memory cell using the first verify voltage and the second verify voltage.