Flash Memory Erase Method Using Dedicated Column Lines for Verification
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Solution Overview
Problem
The existing erase methods for flash memory devices face inefficiencies due to increasing execution time with repeated writes, incomplete post-program steps during sudden shutdowns, and the need for extensive verification to find blank sectors, leading to power consumption and data integrity issues.
Innovation Solution
The method involves pre-programming, erasing, and post-programming memory cells in a flash memory array using additional column lines to record states, allowing for quicker determination of sector completeness and blank sector identification without full erase verification, thereby reducing power consumption and ensuring data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full erase verification is performed to ensure data integrity, then reliability is improved, but loss of time increases
Solution Approach 1:
The patent applies preliminary action by setting specific memory cells in additional column lines to known initial states (first initial state for cells coupled to first column line, second initial state for cells coupled to second column line) before the erase operation. This pre-preparation allows the controller to quickly determine erase completion by checking whether these pre-set cells have been properly erased, without needing to verify all memory cells in the sector.
Solution Approach 2:
The patent segments the verification process by dividing the memory array into regular column lines and additional column lines. The additional column lines contain specifically selected memory cells that serve as verification indicators. By only monitoring these segmented portions rather than the entire memory array, the system achieves fast verification while maintaining data integrity.
2Reliability
If post-program step is performed to repair over-erased memory cells, then reliability is improved, but loss of time increases
Solution Approach 1:
The patent applies self-service by using the additional column lines with pre-set memory cells to automatically indicate when the erase operation is complete and when post-programming is needed. The controller monitors the states of these specific cells and autonomously determines when to stop the erase operation and when to perform post-programming, eliminating the need for time-consuming verification of all memory cells while ensuring over-erased cells are properly repaired.
3Productivity
If additional column lines are used to track sector states, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the additional column lines to serve multiple functions: they track erase operation status, indicate blank sector availability, and provide verification information for post-programming decisions. These additional structures are integrated into the existing memory array architecture and work alongside the regular column lines, allowing the system to achieve enhanced productivity without requiring completely separate tracking mechanisms.
Data Source
AI summary
An erase method for a flash memory is provided. First memory cells of the flash memory are pre-programmed. The first memory cells are disposed in a memory array formed by a plurality of row and column lines. The programmed first memory cells are erased. The erased first memory cells are post-programmed, to repair the over-erased first memory cells. Second memory cells are programmed after the erased first memory cells are post-programmed. The second memory cells are disposed in a first specific column line of the memory array. The first specific column line is arranged after a last column line corresponding to a last valid column address. Third memory cells disposed in a second specific column line of the memory array. The second specific column line is arranged after the last column line and is adjacent to the first specific column line.