Flash Memory Single Program Erase Entity Architecture
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Solution Overview
Problem
Conventional flash memory devices lack the ability to perform single logical cell erasure, restricting them to sector or block-level erasure, which is inefficient and limits byte alterability compared to RAM and hard drives.
Innovation Solution
The implementation of a single program and erase entity as a single logical cell, combining neighboring drain/source regions of two adjacent physical memory cells, allowing for programming and erasure on a single bit or variable bit length basis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional flash memory devices use sector or block-level erasure, then the erasure operation can be performed on larger units, but the erase time increases and byte alterability is limited
Solution Approach 1:
The patent divides the memory array into multiple independent memory cells, each capable of being erased individually. This segmentation allows the erasure operation to be performed on a single logical cell basis rather than requiring sector or block-level erasure, thereby reducing erase time and enabling byte alterability while maintaining the physical constraints of flash memory architecture
2Reliability
If conventional flash memory devices perform erasure on sector or block level, then the operation is simpler to implement, but the device wear increases due to over-erase issues
Solution Approach 1:
The patent applies local quality by enabling erasure operations to be performed selectively on individual logical cells rather than uniformly across entire sectors or blocks. This localized approach allows erasure to be applied only where needed, preventing over-erase of unaffected cells and thereby reducing overall device wear while maintaining operational simplicity through targeted operations
3Adaptability or versatility
If flash memory devices use single logical cell erasure, then the byte alterability improves, but the device complexity increases
Solution Approach 1:
The patent merges multiple physical memory cells to form a single logical cell, where neighboring drain/source regions of two adjacent physical memory cells are combined. This merging approach enables byte alterability through single logical cell erasure while managing device complexity by creating a unified logical structure from multiple physical components, allowing higher-level data manipulation capabilities without proportionally increasing overall system complexity
Data Source
AI summary
Flash memory systems and methods for facilitating a single logical cell erasure in a flash memory device whereby logical cell mapping is changed from using a single physical cell to using pair physical cells, thereby creating a single program and erase entity as a single logical cell. By mapping two adjacent physical cells as a single logical cell, the flash memory device can be programmed and erased on a single bit or variable bit length basis with conventional technologies. Various operations can be performed on a flash device on a basis of the single program and erase entity.