Flash Memory Cell Erase Voltage Control
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Solution Overview
Problem
Conventional flash memory devices face inferior performance and reliability due to improper control of voltages during programming, read, and erase operations, which can lead to inconsistent data storage and retrieval.
Innovation Solution
The implementation of a memory device with a voltage generator and control circuit that applies different voltages to memory cells during erase operations, allowing for separate control of threshold voltages and reduced stress on memory cells by keeping word lines at different voltages, enabling more accurate data programming and reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional voltage control is used during erase operations, then the erase operation can be completed, but the performance and reliability of the flash memory device deteriorates due to improper voltage control
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting voltage levels during the erase operation. Specifically, it changes the voltage applied to word lines from an initial higher voltage (e.g., 20V) to a lower voltage (e.g., 0V or -5V) after a predetermined time period. This temporal variation in voltage parameters enables both effective electron extraction and reduced stress on memory cells, resolving the contradiction between erase effectiveness and device reliability.
Solution Approach 2:
The patent implements periodic action through multi-phase erase operations. The erase process is divided into distinct time periods with different voltage configurations: an initial phase with higher word line voltage for effective erasing, followed by a second phase with reduced or reversed voltage to minimize stress. This periodic voltage modulation achieves both thorough erasure and improved device reliability.
2Productivity
If higher voltages are applied to memory cells during erase operations, then the erase effectiveness improves, but the stress on memory cells increases leading to inferior device performance
Solution Approach 1:
The patent segments the erase operation into distinct time phases with different voltage characteristics. The first time period uses higher voltages (e.g., 20V on word lines) to achieve effective electron extraction from the floating gate, while the second time period uses reduced or reversed voltages (e.g., 0V or -5V) to minimize stress on the memory cell structure. This temporal segmentation allows the system to achieve both erase effectiveness and stress reduction.
Solution Approach 2:
The patent applies beforehand cushioning by implementing a protective voltage phase after the high-voltage erase operation. Following the initial aggressive erase phase, the system switches to lower or negative voltages on word lines to cushion the memory cells from excessive stress and prevent damage accumulation, thereby protecting the device while maintaining erase effectiveness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the performance and reliability of flash memory devices by ensuring accurate data storage and retrieval, reducing stress on memory cells during erase operations and enhancing overall device performance.
Implementation Method 1
an erase operation to extract electrons from the floating gate
Implementation Method 2
keeping word lines at different voltages
Data Source
AI summary
Various embodiments include erasing at least one memory cell of a string of memory cells of a memory device while a control gate of at least one of a first memory cell and a second memory cell of the string of memory cells has a first voltage and while a control gate of each memory cell of a plurality of intermediate memory cells between the first memory cell and the second memory cell has a second voltage. Some embodiments include erase verifying only the first memory cell and second memory cell in a first erase verify operation, and erase verifying the plurality of intermediate memory cells in a second erase verify operation. Other embodiments including additional apparatus, systems, and methods are disclosed.