Multi-bit-cell Flash Memory Page Segmentation for Write Speed
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Solution Overview
Problem
Multi-Level Cell (MLC) flash memory devices experience longer average read and write times and lower reliability compared to Single Level Cell (SLC) devices due to the smaller differences in threshold voltage ranges, leading to potential errors and reduced data retention and endurance, especially when cells are shared across multiple pages.
Innovation Solution
Implementing a method that utilizes blocks with distinct page types in MLC NAND flash memory, where certain pages have faster write or read access speeds, allowing data to be written or read only on the fastest pages while skipping slower pages, effectively emulating Single Bit Cell (SBC) mode within Multi-Bit Cell (MBC) devices to improve performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MLC flash memory stores two bits per cell using four threshold voltage states, then storage density increases, but read and write times increase and reliability decreases
Solution Approach 1:
The patent divides the flash memory block into two distinct page types: fast pages and slow pages. By segmenting the memory structure, the system can selectively write data to fast pages only, avoiding slow pages that would require additional programming cycles. This segmentation resolves the contradiction by isolating the high-density storage capability of MLC from the performance degradation caused by multi-state threshold voltage programming.
Solution Approach 2:
The patent applies local quality by assigning different characteristics to different pages within the same block. Fast pages are optimized for quick write operations with simpler programming sequences, while slow pages are accepted as having inferior performance. By locally optimizing page quality rather than uniformly treating all pages, the system achieves both high storage density and improved write performance for frequently accessed data.
2Quantity of substance
If MLC flash memory uses smaller threshold voltage ranges to store multiple bits, then storage capacity increases, but the difference between states decreases leading to more errors
Solution Approach 1:
The patent segments the memory pages into fast and slow types, using fast pages for data requiring high measurement precision. By directing writes to fast pages with optimized programming sequences, the system ensures that threshold voltage state identification remains accurate even when storing multiple bits per cell, thus resolving the contradiction between storage capacity and measurement precision.
Solution Approach 2:
The patent incorporates read-disturb compensation mechanisms that use feedback to detect and correct threshold voltage shifts. By monitoring voltage drift and applying compensatory programming, the system maintains accurate state identification in MLC cells, resolving the measurement precision issue while preserving multi-bit storage capacity.
3Quantity of substance
If data is written to all pages in sequence, then complete data storage is achieved, but write time increases due to slower pages
Solution Approach 1:
The patent segments the write operation into two paths: fast pages receive immediate writes with optimized sequences, while slow pages are either skipped or handled separately with extended timing. This segmentation allows the system to achieve substantial data storage completeness while minimizing write time by avoiding the bottleneck of slow page programming.
Solution Approach 2:
The patent applies partial action by writing to only the necessary subset of pages (fast pages) for each write operation, rather than sequentially programming all pages. This approach achieves sufficient data storage for most operations while significantly reducing write time by leaving out the time-consuming slow page writes.
Data Source
AI summary
In writing to a block, of a flash memory, that includes pages with different write access or read access speeds, after writing first data to a first page that has fast access, at least one page that has slow access is skipped to write second data to a second page that has fast access.