Flash Memory Control Gate Layout for Floating Gate Isolation
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Solution Overview
Problem
Floating gate bridging in flash memory devices occurs due to insufficient shallow trench isolation between adjacent cells and tapered gate stack profiling during plasma etching, leading to functional failure or low yield during fabrication or quality control testing.
Innovation Solution
Modifying the control gate line geometry by introducing a non-straight edge that is indented away from the common source region, which is achieved through a redesign of the photolithography mask used in the gate stack etching process, ensuring that the isolation strips extend beyond the control gate line edge, thus preventing floating gate bridging without additional fabrication steps or costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional straight control gate line geometry is used, then fabrication process is simple, but floating gate bridging occurs due to insufficient isolation
Solution Approach 1:
The control gate line is designed with an indented edge that breaks the conventional straight symmetric geometry. This asymmetric indentation creates an offset between the control gate line edge and the floating gate edge, ensuring that the isolation strip extends beyond the control gate line and effectively prevents floating gate bridging between adjacent memory cells.
2Reliability
If photolithography mask is redesigned to create indented control gate line, then floating gate bridging is prevented, but manufacturing process complexity increases
Solution Approach 1:
The indentation feature is pre-designed into the photolithography mask before the etching process. This preliminary incorporation of the isolation-enhancing geometry allows the control gate line to be formed with the correct indented shape during the standard photolithography and etching sequence, preventing floating gate bridging without requiring additional fabrication steps or processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces or eliminates floating gate bridging by ensuring that the isolation strips are sufficient to prevent electrical shorting between adjacent flash memory cells, enhancing the reliability and yield of flash memory devices during both fabrication and operation.
Implementation Method 1
achieved through a redesign of the photolithography mask used in the gate stack etching process
Implementation Method 2
tapered gate stack profiling during plasma etching
Data Source
AI summary
A flash memory includes a linear array of flash memory cells having a source region extending along a first direction. Each flash memory cell includes a floating gate disposed adjacent the source region. The linear array of flash memory cells further includes isolation strips disposed between the floating gates of the flash memory cells. An erase gate line extends along the first direction and is disposed over the source region. A control gate line extends along the first direction and is disposed over the isolation strips and over the floating gates of the flash memory cells. The control gate line has a non-straight edge proximate to the source region that is indented away from the source region at least where the control gate line is disposed over the isolation strips.