3D Flash Memory Gate Stack Layout for Higher Cell Density
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Solution Overview
Problem
Current three-dimensional NAND flash memory technologies face challenges in increasing memory cell density, which limits the integration density of memory devices.
Innovation Solution
A flash memory device and manufacturing method that include a gate stack structure with alternately stacked gate and insulating layers, channel pillars electrically isolated by insulating pillars, and charge storage or phase change memory regions coupled to the channel pillars, allowing for closer arrangement of memory cells and increased density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional three-dimensional NAND flash memory structures are used, then manufacturing process is relatively simple, but memory cell density is low
Solution Approach 1:
The gate electrode is segmented into multiple distinct gates (first gate, second gate, third gate) positioned at different heights within the gate stack structure. This segmentation allows independent control of different channel regions, enabling higher density memory cells through multi-level cell architectures while maintaining manageable manufacturing complexity through modular fabrication processes
Solution Approach 2:
The invention transitions from planar or simple 3D structures to a multi-dimensional gate stack architecture where gates are arranged vertically at different elevations. This dimensional expansion allows memory cells to be packed more densely by utilizing vertical space efficiently, with multiple gates controlling different segments of the channel pillar to achieve higher storage capacity per unit area
2Quantity of substance
If memory cells are arranged closer together to increase density, then memory cell density increases, but manufacturing precision requirements increase
Solution Approach 1:
The gate stack structure is formed with predetermined spatial relationships between multiple gates and channel pillars before final memory cell patterning. sacrificial layers are positioned in advance to define precise locations for charge storage structures and channel pillars, ensuring accurate alignment even when memory cells are densely packed. This preliminary structuring reduces the precision burden on subsequent fabrication steps
Solution Approach 2:
Sacrificial layers serve as intermediary structures that facilitate precise positioning of channel pillars and charge storage structures relative to the multi-level gates. These temporary structures guide the formation process, ensuring correct spatial relationships are established, and are removed after serving their alignment function, thereby enabling high-density arrangements without excessive precision requirements
Data Source
AI summary
Provided is a flash memory device including a gate stack structure, at least three channel pillars, a charge storage structure, at least three source line, and at least three bit lines. The gate stack structure is disposed above a substrate. The gate stack structure includes a plurality of gate layers and a plurality of insulating layers stacked alternately each other. The at least three channel pillars extend through the gate stack structure. The at least three channel pillars are electrically isolated from one another. The charge storage structure is disposed between the plurality of gate layers and the at least three channel pillars. The at least three source line are disposed below the gate stack structure and electrically connected to the at least three channel pillars. The at least three bit lines are disposed above the gate stack structure, and electrically connected to the at least three channel pillars.