Flash Memory Sequential Read Overlapping Precharge
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Solution Overview
Problem
The speed of read operations in flash memory devices is limited by the time required for bit-line precharge and equalization, which hampers the efficiency of sequential read operations.
Innovation Solution
Implementing overlapping read cycles to initiate bit-line precharge and equalization for the next memory cell address before the completion of the current read cycle, and partitioning the memory cell array into sub-banks to enable early activation of word-lines, thereby reducing read cycle time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional sequential read operations are used with complete precharge and equalization cycles, then read accuracy is maintained, but read speed is limited due to the time required for bit-line precharge and equalization
Solution Approach 1:
The patent applies preliminary action by initiating bit-line precharge and equalization for the next memory cell address before the current read cycle completes. This overlapping approach allows the system to perform preparation work in advance, eliminating the need to wait for complete precharge and equalization before starting the next read operation, thereby reducing total read time while maintaining read accuracy
Solution Approach 2:
The patent implements continuity of useful action by overlapping read cycles so that bit-line precharge and equalization operations continue without interruption. While one bit-line is being sensed, another bit-line is being precharged and equalized in parallel, ensuring that useful work is always being performed and eliminating idle waiting time between sequential read operations
2Speed
If memory cell array is accessed sequentially without partitioning, then device complexity is low, but word-line activation time limits read speed
Solution Approach 1:
The patent applies segmentation by partitioning the memory cell array into multiple sub-banks. This division allows different sub-banks to be accessed and activated independently and in parallel, reducing the time required for word-line activation across the entire array. Each sub-bank can be precharged and equalized simultaneously, thereby increasing read speed while managing device complexity through modular organization
Data Source
AI summary
A flash memory device implements a sequential read method using overlapping read cycles to initiate the bit-line precharge and equalization operation for a next memory cell address prior to the completion of the read cycle of the current memory cell address. More specifically, the sequential read method implements overlapping read cycle where the bit-line precharge and equalization operation is started for a memory cell of the next address while the memory cell of the current address is being read out. In this manner, the read speed for the sequential read operation of the flash memory device is improved. In some embodiments, the memory cell array for each input-output (I/O) of the flash memory device is partitioned into two sub-banks to further reduce the read cycle time by enabling early activation of the word-line for the next sub-bank.