Flash Memory Page Buffer Transistor Layout Alternating Symmetry

Solution Overview

Problem

Conventional flash memory devices require large spacing intervals between high voltage transistors in page buffer circuits due to alternating bias voltages, leading to inefficient layout and reduced transistor density.

Innovation Solution

The proposed solution involves a layout method where high voltage transistors in a flash memory device are series connected in a columnar arrangement with alternating source/drain symmetry, allowing all column adjacent transistors to receive the same bias voltage during an erase operation, thereby reducing the spacing interval between them.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If large spacing intervals are used between high voltage transistors to accommodate alternating bias voltages, then transistor reliability is improved, but layout area increases and transistor density decreases

Engineering Contradiction:

Improvetransistor reliabilityVSAvoidlayout area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the bias voltage supply for adjacent transistors by connecting them to the same voltage line. Specifically, even-numbered transistors (T2, T4, T6...) are connected to one voltage line while odd-numbered transistors (T1, T3, T5...) are connected to another voltage line, allowing alternating transistors to share the same bias voltage potential and reducing spacing requirements

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces a new dimensional arrangement by organizing transistors in alternating odd/even patterns across multiple voltage lines. This dimensional reorganization allows transistors that would traditionally require large spacing to be placed closer together in a systematic alternating pattern, effectively utilizing the voltage line dimension to resolve spacing conflicts

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If large spacing intervals are used between high voltage transistors to accommodate alternating bias voltages, then transistor reliability is improved, but transistor density decreases

Engineering Contradiction:

Improvetransistor reliabilityVSAvoidtransistor density

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent merges the bias voltage supply for adjacent transistors by connecting them to the same voltage line. Specifically, even-numbered transistors (T2, T4, T6...) are connected to one voltage line while odd-numbered transistors (T1, T3, T5...) are connected to another voltage line, allowing alternating transistors to share the same bias voltage potential and reducing spacing requirements

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces a new dimensional arrangement by organizing transistors in alternating odd/even patterns across multiple voltage lines. This dimensional reorganization allows transistors that would traditionally require large spacing to be placed closer together in a systematic alternating pattern, effectively utilizing the voltage line dimension to resolve spacing conflicts

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Reliability

If conventional layout methods are used with alternating bias voltages, then voltage isolation is improved, but layout efficiency decreases

Engineering Contradiction:

Improvevoltage isolationVSAvoidlayout efficiency

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent segments the voltage supply system into two distinct voltage lines: one serving even-numbered transistors and another serving odd-numbered transistors. This segmentation allows for systematic voltage distribution while maintaining proper isolation through the alternating connection pattern, improving layout efficiency without compromising voltage isolation

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimensional arrangement by organizing transistors in alternating odd/even patterns across multiple voltage lines. This dimensional reorganization allows transistors that would traditionally require large spacing to be placed closer together in a systematic alternating pattern, effectively utilizing the voltage line dimension to resolve spacing conflicts

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS8040726B2Flash memory device and layout method of the flash memory device

Publication Date: 2011.10.18 SAMSUNG ELECTRONICS CO LTD

AI summary

Provided is a flash memory device including a plurality of page buffer high voltage transistors. The plurality of high voltage transistors are operatively associated with a page buffer circuit, wherein each high voltage transistor includes; a gate pattern separating a first pattern from a second pattern. The first and second patterns extend in parallel and serve as respective source/drain regions, and the first pattern is floated and the second pattern receives an erase voltage during an erase operation. A first set of high voltage transistors is series connected in a columnar arrangement, such that column adjacent high voltage transistors are laid out with alternating source/drain symmetry in the columnar direction.