Flash Memory Page Grouping for Error Correction in SSDs

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Solution Overview

Problem

Conventional approaches to error management in flash memory, particularly in multi-level cell (MLC) flash memories, are inefficient in achieving low uncorrectable error rates over the total service life and traffic loads required in enterprise storage environments, leading to degradation in signal-to-noise ratio and reduced reliability.

Innovation Solution

The techniques involve grouping flash memory pages across multiple dies and managing them to reduce error floors and flares, allowing for efficient error correction and seamless operation despite die failures, using a method that includes organizing memory into block grids with page grids and page stripes, and employing adaptive error correction coding to minimize the impact of die failures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional BCH error correction coding is used in MLC flash memory, then the implementation is simple and cost-effective, but the uncorrectable error rate becomes too high for enterprise storage requirements

Engineering Contradiction:

Improveuncorrectable error rateVSAvoiderror correction complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the error correction task into two independent stages: first applying BCH coding at the page level, then applying Reed-Solomon coding at the block level. This segmentation allows each coding scheme to operate optimally within its domain, achieving enterprise-grade reliability without requiring a single overly complex code

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent merges two different error correction coding schemes (BCH and Reed-Solomon) into a unified two-stage system. The BCH code handles page-level errors while Reed-Solomon handles block-level errors, creating a combined system that achieves reliability targets that neither code could achieve alone

Inventive Principle:

Principle #5Merging (Combining)

2Quantity of substance

If flash memory density is increased with decreasing process technology, then storage capacity improves, but signal-to-noise ratio decreases due to charge loss, crosstalk, and thinner insulation

Engineering Contradiction:

Improvestorage capacityVSAvoidsignal-to-noise ratio

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent transitions from single-page error correction to multi-page block-level error correction. By organizing pages into blocks and applying Reed-Solomon coding across the entire block, the system can tolerate errors that affect individual pages while maintaining overall data integrity, effectively adding a dimensional layer of protection

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent预先 allocates spare pages within each block that are not used for user data but are reserved for error correction and data recovery. These spare pages act as a cushion that absorbs the impact of failures in user pages, allowing the system to maintain reliability even as density increases and error rates rise

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

3Ease of manufacture

If MLC flash memory is used instead of SLC, then cost is reduced and storage density is increased, but program/erase cycle lifetime is significantly reduced

Engineering Contradiction:

Improvecost and densityVSAvoidprogram/erase cycle lifetime

Core Design Contradiction:

Ease of manufactureVSDuration of action of stationary object

Solution Approach 1:

The patent changes the error correction parameters dynamically based on the flash memory's wear state. As MLC cells degrade through program/erase cycles, the system can adjust the Reed-Solomon code strength and utilize spare pages more aggressively, extending the usable life of the memory beyond manufacturer specifications

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent treats individual flash pages as disposable units that can fail without compromising the entire block. By using Reed-Solomon coding to reconstruct data from remaining good pages, the system can tolerate the failure of multiple pages, effectively making individual pages expendable and extending overall system lifetime

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

4Reliability

If more ECC parity data is stored per page, then error correction capability is improved, but storage efficiency decreases and write amplification increases

Engineering Contradiction:

Improveerror correction capabilityVSAvoidstorage efficiency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent merges the error correction capacity across multiple pages by creating blocks that combine several pages with their respective BCH parity. The Reed-Solomon code then operates on this combined data structure, allowing error correction capability to be shared across the entire block rather than being duplicated in each page, thereby improving storage efficiency

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS9208018B1Systems and methods for reclaiming memory for solid-state memory

Publication Date: 2015.12.08 IP GEM GRP LLC

AI summary

Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be reliably implemented using various types of memory cells, including relatively inexpensive multi-level cell flash. One embodiment intelligently coordinates remapping of bad blocks with error correction code control, which eliminates the tables used to avoid bad blocks.