Flash Memory Post-Write Read Sampling for Error Management
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Solution Overview
Problem
Conventional error correction codes (ECC) in flash memory systems are resource-intensive and designed for worst-case error rates, leading to performance degradation and high overhead, as they need to correct a large number of error bits, especially towards the end of a device's life, which is not typically required for most of the device's operational life.
Innovation Solution
A flash memory system is configured with a first portion for efficient storage and a second portion with lower error rates, where data is written to the higher density second portion and then checked for excessive errors; if errors exceed a predetermined limit, the data is rewritten to the less error-prone first portion, allowing for a smaller and more efficient ECC to be used, reducing the number of error bits that need correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC is designed for worst-case error rates, then reliability is improved, but device complexity and computational load increase
Solution Approach 1:
The patent changes the parameter of error rate assumption from worst-case to typical operational error rates. By designing ECC based on actual observed error rates rather than theoretical worst-case scenarios, the system achieves adequate reliability with reduced computational complexity and smaller ECC codes.
Solution Approach 2:
The patent applies partial action by implementing ECC capacity sufficient for typical error rates rather than full capacity needed for worst-case scenarios. This provides adequate error correction for the majority of operational conditions without the excessive complexity required for rare worst-case events.
2Productivity
If higher density storage is used, then productivity is improved, but manufacturing precision requirements increase due to smaller error margins
Solution Approach 1:
The patent changes the operational parameters of memory cells to optimize for higher density while maintaining acceptable error rates. By adjusting voltage levels, programming pulses, and read thresholds, the system achieves high-density storage with manageable error margins that can be corrected by simplified ECC.
3Reliability
If post-write read is performed on all data, then reliability is improved, but loss of time increases
Solution Approach 1:
The patent applies partial action by performing post-write read verification only on a sample of written data rather than all data. By selecting representative samples for verification, the system achieves adequate confidence in data integrity with significantly reduced time overhead compared to verifying every byte.
Data Source
AI summary
Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. An error management provides reading and checking the copy after copying to the second portion. If the copy has excessive error bits, it is repeated in a different location either in the second or first portion. The reading and checking of the copy is accelerated by reading only a sample of it. The sample is selected from a subset of the copy having its own ECC and estimated to represent a worst error rate among the copy it is sampling. One embodiment has the sample taken from one bit of each multi-bit memory cell of a group.