Parallel Pre-code System for Flash Memory Defect Mapping
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Solution Overview
Problem
Existing methods for pre-coding flash memory in pre-code products are inefficient, as they often require manual coding and do not account for defect memory blocks, leading to increased manufacturing costs and reduced functionality.
Innovation Solution
A pre-code system that includes a pre-code machine and devices with an address decoder and alternative logic circuit, which uses an address mapping table to map defect physical addresses to replacing addresses, enabling parallel pre-coding of multiple devices simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If manual pre-coding method is used, then pre-coding operation can be performed, but pre-coding efficiency is low and manufacturing cost is high
Solution Approach 1:
The patent implements pre-coding operation during the manufacturing process before the flash memory devices are shipped to customers. By performing the pre-coding operation in advance on defect-free blocks, the system eliminates the need for customers to perform time-consuming and complex pre-coding operations, thereby improving pre-coding efficiency and reducing manufacturing costs through automated parallel processing
Solution Approach 2:
The patent combines multiple pre-coding operations into a single parallel processing system. The pre-code machine simultaneously performs pre-coding on multiple flash memory devices using shared resources including the pre-code data buffer, address mapping table, and control logic, thereby achieving high-throughput manufacturing with reduced cost per device
2Reliability
If defect memory blocks are not mapped, then address management is simple, but product functionality is reduced due to unusable defect blocks
Solution Approach 1:
The patent introduces an address mapping table as an intermediary data structure that maps logical addresses to physical addresses in flash memory devices. This mapping table, stored in the pre-code device, enables the system to transparently redirect access from defect blocks to their corresponding replacement blocks, thereby maintaining full product functionality while managing defect blocks efficiently
Solution Approach 2:
The patent creates a virtual copy of the address space through the address mapping table. Instead of physically reorganizing data during pre-coding, the system creates a logical mapping that copies the address translation information, allowing defect blocks to be replaced with functional blocks while maintaining the original address structure for the host system
3Speed
If parallel pre-coding operation is not implemented, then device complexity is low, but pre-coding speed is slow
Solution Approach 1:
The patent segments the pre-coding operation into multiple parallel channels, each capable of independently processing one or more flash memory devices. The pre-code machine includes multiple pre-code data buffers and address decoders that operate simultaneously on different devices, thereby achieving high-speed parallel pre-coding while keeping each individual processing channel relatively simple
Data Source
AI summary
A pre-code device includes firstly memory circuit, an address decoder, and an alternative logic circuit. The first memory circuit includes a number of memory blocks and at east a replacing block. The memory blocks are pointed by a number of respective physical addresses. The replacing block is pointed by a replacing address. The address decoder decodes an input address to provide a pre-code address. The alternative logic circuit looks up an address mapping table, which maps defect physical address among the physical addresses to the replacing address, to map the pre-code address to the replacing address when the pre-code address corresponds to the defect physical address. The alternative logic circuit correspondingly pre-codes the pre-code data to the replacing block.