Flash Memory Programming via Source-to-Drain Biasing
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Solution Overview
Problem
Conventional flash memory devices experience interference and incomplete programming due to high word line voltage loads, leading to unreliable memory devices as a result of the pass disturb phenomenon during programming.
Innovation Solution
A method is introduced where a memory cell is programmed at a low boosting potential level by excluding it from the channel boosting region through sequential programming from the source to the drain within a memory cell string, using different voltages on the source and drain sides to prevent interference and maintain a high self-boosting potential level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high gate voltage is applied to all unselected word lines to maintain the channel at a high boosting potential level, then the programming of selected memory cells is facilitated, but a pass disturb phenomenon occurs at unselected memory cell strings resulting in unreliable memory devices
Solution Approach 1:
The patent divides the word lines into two distinct groups: selected word lines that receive high voltage to enable programming, and unselected word lines that receive low voltage to prevent pass disturb. This segmentation allows different voltage levels to be applied to different parts of the memory array simultaneously, resolving the contradiction between facilitating programming and preventing interference.
Solution Approach 2:
The patent applies different voltage characteristics to different regions of the memory device. Specifically, selected word lines are maintained at high voltage locally to enable electron tunneling in selected memory cells, while unselected word lines are maintained at low voltage locally to prevent unwanted effects. This local differentiation of voltage quality eliminates the pass disturb phenomenon while preserving programming functionality.
2Productivity
If the potential difference between word lines and channel is maximized to facilitate FN tunneling, then programming efficiency is improved, but interference between memory cells increases
Solution Approach 1:
The patent segments the memory cell strings into selected and unselected groups, applying different voltage conditions to each group. Selected memory cell strings receive high word line voltage to maximize potential difference and facilitate FN tunneling for efficient programming, while unselected memory cell strings receive low word line voltage to minimize potential difference and prevent interference. This spatial segmentation resolves the contradiction between programming efficiency and interference prevention.
Solution Approach 2:
The patent creates local variations in electrical potential across different regions of the memory array. In selected regions, high potential difference is maintained to enable efficient electron tunneling and programming. In unselected regions, low potential difference is maintained to prevent unwanted electron movement and interference. This local quality control allows simultaneous optimization of programming efficiency and interference reduction.
Data Source
AI summary
A method for programming a flash memory device includes applying a program bias to a memory cell of a plurality of memory cells within a memory cell string. Each memory cell string comprises a source select line, a plurality of memory cells and a drain select line. A first pass bias is applied to at least one of the memory cells in a source select line direction relative to the memory cell to which the program bias has been applied. A second pass bias is applied to the memory cells in a drain select line direction relative the memory cell(s) to which the first pass bias has been applied.