Flash Memory Programming Control Logic for Step Increment Adaptation
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Solution Overview
Problem
Flash memory devices face challenges in precisely controlling threshold-voltage distributions during programming, leading to inefficiencies in programming speed and performance, particularly due to the limitations of incremental step pulse programming (ISPP) and convergence modes.
Innovation Solution
The implementation of a flash memory device with a control logic block that adjusts the bit line voltage, number of cells to be programmed, programming time, and bulk voltage based on selected step increments, allowing for variable control during both ISPP and convergence programming modes, optimizing programming performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the step increment of the programming voltage is made smaller to narrow the threshold-voltage distributions, then the manufacturing precision is improved, but the productivity decreases due to the increased number of programming loops
Solution Approach 1:
The patent implements dynamic adjustment of programming conditions by varying the bit line voltage, programming time, and bulk voltage based on the selected step increment. The control logic block modifies these parameters in response to different step increment values, allowing the system to adapt programming conditions to achieve both narrow threshold-voltage distributions and efficient programming speed.
Solution Approach 2:
The patent changes multiple programming parameters simultaneously - bit line voltage, programming time, and bulk voltage - in response to the selected step increment. This coordinated parameter adjustment allows the system to optimize both precision and speed by matching programming conditions to the desired step increment value.
2Productivity
If the step increment of the programming voltage is increased to improve programming speed, then the productivity is improved, but the manufacturing precision deteriorates due to wider threshold-voltage distributions
Solution Approach 1:
The system dynamically adjusts programming conditions based on the step increment value. When a larger step increment is selected for faster programming, the control logic block compensates by modifying bit line voltage, programming time, and bulk voltage to maintain threshold-voltage distribution precision.
Solution Approach 2:
The patent coordinates changes in multiple parameters - bit line voltage, programming time, and bulk voltage - in response to the selected step increment. This allows the system to achieve fast programming with large step increments while maintaining precision through compensatory parameter adjustments.
3Device complexity
If fixed programming conditions are used in ISPP mode, then the device complexity is reduced, but the manufacturing precision and productivity cannot be optimized simultaneously
Solution Approach 1:
The patent introduces dynamic control of programming conditions through a control logic block that responds to the selected step increment. This adds adaptability to the ISPP mode, allowing the system to optimize precision and speed without significantly increasing device complexity.
Solution Approach 2:
The system enables variable programming parameters (bit line voltage, programming time, bulk voltage) that are adjusted based on the selected step increment. This provides optimization capability while maintaining the relatively simple ISPP control structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances programming performance by allowing for flexible adjustments in programming conditions, improving the precision and speed of threshold-voltage distributions, thereby optimizing the programming process.
Implementation Method 1
A high voltage (or programming voltage), e.g., about 10V, is applied to the control gate and a voltage (e.g., 5 ̃6V) for inducing hot electrons is applied to the drain of the NOR flash memory cell. The voltages applied to the control gate and the drain act to induce hot electrons. Such hot electrons are accumulated in the floating gate.
Implementation Method 2
In erasing the NOR flash memory cell, a large voltage gap is set between the control gate and the substrate (or bulk), which releases electrons from the floating gate through the Fowler-Nordheim (F-N) tunneling effect.
Data Source
AI summary
A flash memory device includes a flash memory cell array having flash memory cells arranged with word and bit lines, a word line driver circuit configured to drive the word lines at a selected step increment during a programming operation, a bulk-voltage supply circuit configured to supply a bulk voltage into a bulk of the flash memory cell array and a writing circuit configured to drive the bit lines selected by conditions during a programming operation. A control logic block is configured to control the writing circuit and the bulk-voltage supply circuit during the programming operation. The control logic block is configured to cause the writing circuit and/or the bulk-voltage supply circuit to change at least one of the conditions of the writing circuit and/or the bulk voltage responsive to the selected step increment.