Flash Memory Partial Block Pure Data Padding

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Solution Overview

Problem

In NAND flash memory systems, partial blocks with blank word lines lead to higher read bit error rates due to voltage mismatches, requiring extensive padding with random data to mitigate errors, which increases system resource usage and degrades performance as the number of word lines expands.

Innovation Solution

Implementing pure data padding, where a single predefined level of pure data is written to specific word lines adjacent to the boundary word line, reducing the need for extensive padding and minimizing system performance burden by relocating the voltage distribution to match closed block conditions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If random data padding is used to fill blank word lines in partial blocks, then read bit error rates are reduced, but system performance degrades and resource usage increases

Engineering Contradiction:
Improveread bit error rateVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent changes the data pattern parameter from random data to pure data (repeating patterns of 0s and 1s). This parameter change reduces the amount of data that needs to be written to blank word lines while still achieving voltage distribution optimization, thereby improving system performance while maintaining reliability

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent applies partial padding by only filling blank word lines with pure data patterns rather than completely filling all blank word lines with random data. This partial action is sufficient to achieve the voltage distribution optimization needed for reliable reads without the excessive resource consumption of complete random data padding

Inventive Principle:
Principle #16Partial or excessive action

2Stability of the object's composition

If extensive padding with random data is applied to all word lines, then voltage distribution is optimized, but the quantity of data writing increases significantly

Engineering Contradiction:
Improvevoltage distributionVSAvoidquantity of data writing
Core Design Contradiction:
Stability of the object's compositionVSQuantity of substance

Solution Approach 1:

The patent changes the data content parameter from random data to pure data patterns. This allows the same voltage distribution optimization to be achieved with significantly less data writing, as pure data patterns require fewer write operations compared to random data padding across all word lines

Inventive Principle:
Principle #35Parameter changes

3Reliability

If traditional random data padding is used, then read errors are mitigated, but device complexity and processing time increase

Engineering Contradiction:
Improveread error mitigationVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent changes the padding data parameter from random to pure data patterns, which can be written more efficiently and require less processing time. The pure data patterns are simpler to generate and write compared to random data, reducing the time loss while maintaining the same error mitigation effectiveness

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20240395329A1Padding in flash memory blocks
Publication Date: 2024.11.28 MICRON TECHNOLOGY INC
  • US20240395329A1 patent drawing
  • US20240395329A1 patent drawing
  • US20240395329A1 patent drawing

AI summary

A method includes determining a boundary word line in a partial block of a flash memory device, where the partial block includes blank word lines after the boundary word line; determining a single predefined level of pure data to write in at least one of the blank word lines after the boundary word line; and writing the single predefined level of pure data to at least one of the blank word lines after the boundary word line.