Flash Memory Redundancy Logic for Autonomous Yield Repair
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Solution Overview
Problem
The existing techniques for improving yield and productivity in FLASH memory devices through redundancy increase testing time and complexity, requiring extensive resources and silicon area, making them unsuitable for standalone devices.
Innovation Solution
An automatic redundancy system utilizing the existing microprocessor system to detect and substitute failed memory cells without external test machine intervention, reducing testing time and silicon area usage by implementing a logic structure for mapping failures to redundant elements within the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If row, column, and sector redundancy techniques are implemented to increase yield, then the yield is improved, but the testing time on wafer increases
Solution Approach 1:
The memory device performs self-testing and self-repair operations using integrated BIST logic and spare rows/columns/sectors. The device autonomously detects failures, maps them to redundant resources, and repairs itself without requiring external test machine intervention for each individual operation, thereby reducing overall testing time while maintaining high yield through redundancy
Solution Approach 2:
Spare rows, columns, and sectors are pre-configured and reserved during device fabrication. The BIST logic is pre-programmed with redundancy mapping algorithms. When failures are detected during testing, the device can immediately activate pre-prepared redundant resources without requiring time-consuming external reconfiguration, thus improving yield while minimizing testing time overhead
2Reliability
If complex redundancy mapping procedures are implemented to repair failed elements, then the yield is improved, but the device complexity increases
Solution Approach 1:
The BIST logic includes integrated failure detection and redundancy mapping capabilities that operate autonomously within the memory device. The system self-manages the complex redundancy procedures by automatically detecting failures, determining appropriate spare resources, and performing mapping operations internally, thereby achieving high yield improvement while containing device complexity through self-contained functionality
Solution Approach 2:
The patent combines failure detection, failure storage, redundancy rule application, and mapping operations into an integrated BIST system within the memory device. By merging these previously separate functions into a unified self-contained system, the complexity is consolidated and managed more efficiently, achieving yield improvement without proportionally increasing overall device complexity
3Productivity
If dedicated BIST and BISR structures are integrated to simplify test machine operations, then the productivity is improved, but the silicon area increases
Solution Approach 1:
The BIST logic is designed to perform multiple functions including failure detection across different memory structures (rows, columns, sectors), failure storage, redundancy mapping, and self-repair coordination. By making the BIST system multi-functional, the silicon area required is optimized while still achieving the productivity improvements needed for efficient fabrication testing
Solution Approach 2:
Instead of implementing separate dedicated hardware for each testing and repair function, the patent uses a unified BIST logic that copies and reuses the same structural elements (sense amplifiers, decoders, control logic) for multiple purposes. This approach reduces silicon area while maintaining the functionality needed to improve fabrication productivity through integrated self-testing and self-repair
Data Source
AI summary
An automatic redundancy system may exploit an existing microprocessor management system on chip for carrying out autonomously, without communicating with an external testing machine, the operations of: writing data in the memory array according to one or more pre-established test patterns, verifying data successively read from the memory array, and substituting failed elements of the memory array with equivalent redundancy structures. A logic structure may detect and store memory array failures upstream of the output data path. Thereby, data collection relating to failures may be accomplished more quickly and without any interaction with the testing machine apart from communicating the end of the execution of the redundancy process.