Flash Memory Select Gate Width via Multi-Mask Patterning
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Solution Overview
Problem
Existing lithographic techniques are inadequate for implementing optimal designs in non-volatile semiconductor memory devices with ever-decreasing channel lengths, particularly in achieving minimum line space patterns and preventing current leakage, as they constrain memory elements and select gates to the same feature size.
Innovation Solution
A method involving the use of multiple photomasks to create flexible design patterns, where patterns from first and second photomasks are transferred to a photoresist layer, forming gaps and protective regions, allowing for the formation of memory element structures and select gates with varying widths, thereby preventing current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If minimum line space patterns are used with fixed photomask openings, then manufacturing precision is improved, but select gate width cannot be increased to prevent current leakage
Solution Approach 1:
The patent divides the patterning process into multiple steps using separate photomasks. The first photomask creates minimum line space patterns for memory elements, while the second photomask adds wider select gate regions. This segmentation allows each photomask to optimize for its specific function, resolving the contradiction between minimum feature size and select gate width requirements.
Solution Approach 2:
The patent transitions from a single-layer photomask approach to a multi-layer photomask system. By adding the dimension of multiple patterning layers, the process can simultaneously achieve minimum line space patterns (first photomask) and wider select gates (second photomask), effectively resolving the dimensional constraint of fixed feature size.
2Manufacturing precision
If the same feature size is used for both memory elements and select gates, then lithographic constraints are satisfied, but design flexibility is reduced
Solution Approach 1:
The patent introduces dynamic feature sizing where select gates can have different widths than memory elements. The second photomask enables variable select gate widths (e.g., 1.5F or 2F) while maintaining the minimum F feature size for memory elements, providing design flexibility without compromising lithographic manufacturability.
Solution Approach 2:
The patent applies different feature sizes to different regions of the device. Memory elements maintain the minimum F feature size for optimal density, while select gates are locally enlarged to 1.5F or 2F to prevent current leakage. This local differentiation resolves the contradiction between uniform lithographic constraints and varied functional requirements.
3Productivity
If channel length is decreased to increase memory density, then productivity is improved, but existing lithographic techniques become inadequate
Solution Approach 1:
The patent performs preliminary patterning actions using multiple photomasks at larger effective feature sizes. The first photomask establishes minimum line space patterns, and the second photomask pre-defines select gate regions before final etching. This preliminary multi-step patterning enables subsequent fabrication of smaller channel length devices (45-55 nm) that would be difficult to achieve with single-step lithography.
Data Source
AI summary
A non-volatile memory device having memory elements with a channel length of, e.g., 45-55 nm or less, is fabricated using existing lithographic techniques. In one approach, patterns of first and second photomasks are transferred to the same photoresist layer. The first photomask can have openings with a given feature size F that are spaced apart by the feature size F, for instance. The second photomask has an opening which is sized to create a desired inter-select gate gap, such as 3 F or 5 F. A third photomask is used to provide protective portions in a second photoresist layer over the select gate structures. The final structure has memory elements of width F spaced apart by a distance F, and select gates of width 3 F spaced apart by 3 F or 5 F. In another approach, the patterns of three photomasks are transferred to respective photoresist layers to create an analogous final structure.