Flash Memory Selection-Decoding Circuit Power Management

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Solution Overview

Problem

Flash memory systems face challenges in reducing power consumption, which is essential for energy-efficient computing and electronic devices.

Innovation Solution

The implementation of a selection-decoding circuit path using pull-up and pull-down circuits to save values at output nodes during power save or shutdown modes, allowing the main power source to be shut down while maintaining data integrity, along with low power read reference generation and address/data encoding/decoding/scrambling techniques.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the main power source is shut down during power save or shutdown modes, then power consumption is reduced, but data at output nodes is lost

Engineering Contradiction:

Improvepower consumptionVSAvoiddata loss at output nodes

Core Design Contradiction:

Use of energy by moving objectVSLoss of information

Solution Approach 1:

The patent applies preliminary action by activating pull-up or pull-down circuits before shutting down the main power source. These circuits pre-establish the desired voltage state (high or low) at output nodes, ensuring that when power is removed, the nodes maintain their correct logical state without data loss. This preparatory action prevents the information loss that would otherwise occur during power-down modes.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If pull-up and pull-down circuits are used to maintain data during power-down, then data integrity is preserved, but circuit complexity increases

Engineering Contradiction:

Improvedata integrity during power-downVSAvoidcircuit complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by selectively applying pull-up or pull-down circuits only to specific output nodes that require data retention during power-down modes, rather than uniformly across the entire circuit. This targeted approach maintains data integrity where needed while minimizing the addition of circuitry, thus balancing reliability improvement with controlled complexity increase.

Inventive Principle:

Principle #3Local quality

3Device complexity

If conventional decoding circuits are used during power-down modes, then simple circuit design is maintained, but power consumption increases

Engineering Contradiction:

Improvecircuit design simplicityVSAvoidpower consumption during power-down

Core Design Contradiction:

Device complexityVSUse of energy by moving object

Solution Approach 1:

The patent applies the taking out principle by extracting and isolating the essential data retention function from the main power-consuming decoding circuitry. By using simple pull-up or pull-down circuits that can operate with minimal or no main power source, the patent separates the data retention function from the full decoding operation, thereby reducing power consumption during power-down modes while maintaining the necessary functionality.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentEP3680903A1Low power operation for flash memory system

Publication Date: 2020.07.15 SILICON STORAGE TECHNOLOGY INC

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AI summary

The present invention relates to a circuit and method for low power operation in a flash memory system. In disclosed embodiments of a selection-decoding circuit path, pull-up and pull-down circuits are used to save values at certain output nodes during a power save or shut down modes, which allows the main power source to be shut down while still maintaining the values.