Flash Memory Sense Amplifier Synchronization
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Solution Overview
Problem
Dual job FLASH memory devices face disturbances during simultaneous read and modify operations due to current absorption peaks from common supply nodes, affecting data accuracy, especially when turning on or off sense amplifiers, which are critical for both operations.
Innovation Solution
The method involves extending the duration of the verify operation for data modification beyond the critical discrimination phase of sense amplifiers and delaying the turn-on or turn-off signals of sense amplifiers to prevent coincident operations, ensuring no disturbance occurs during critical phases by using a pass-gate and latch system or adjustable delay circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If sense amplifiers are turned on or off during simultaneous read and verify operations, then power consumption is reduced and access time is improved, but current absorption peaks cause disturbances on common supply nodes that affect data accuracy
Solution Approach 1:
The patent applies preliminary action by extending the verify operation duration beyond the critical discrimination phase and delaying the turn-on or turn-off signals of sense amplifiers. This ensures that sense amplifier switching occurs outside the critical discrimination window, preventing current absorption peaks from disturbing the read operation while still achieving power savings and fast access times.
2Reliability
If the duration of verify operation is extended beyond the critical discrimination phase, then disturbances during critical phases are prevented, but operation cycle duration increases
Solution Approach 1:
The verify operation is extended in advance beyond the critical discrimination phase to preemptively prevent disturbances. By scheduling the verify operation to complete before the critical phase or to overlap only in non-critical portions, the patent ensures data accuracy without excessive time penalty.
Solution Approach 2:
The patent dynamically adjusts the timing of sense amplifier turn-on and turn-off signals based on the operation phase. The delay circuits or control logic modify the timing characteristics in real-time to avoid the critical discrimination window, optimizing both reliability and speed.
3Speed
If sense amplifiers are kept constantly powered to avoid turn-on/turn-off delays, then access time is improved, but power consumption increases
Solution Approach 1:
Instead of constant power supply, the patent uses periodic action by turning sense amplifiers on and off in synchronization with operation phases. The amplifiers are powered only when needed for read or verify operations, reducing overall power consumption while maintaining fast access times through optimized timing.
Solution Approach 2:
The patent preliminarily plans the power state transitions of sense amplifiers to occur outside critical phases. By anticipating when amplifiers need to be active and preparing their power state in advance, the system achieves fast access without continuous power consumption.
Data Source
AI summary
A method is for reducing possible errors in execution of simultaneous read and verify operations of data being modified in first and second different partitions of a memory device caused by turning on or off of a first partition's bank of sense amplifiers while a critical discrimination phase is being carried out by the second partition's bank of sense amplifiers. The method may include establishing an augmented duration of one of the read and verify operations exceeding a duration of the first partition's critical discrimination phase. The method may conditionally delay generation of a turn on or turn off signal of the first partition by a time determined by a command of termination, or by a beginning of the critical discrimination phase of the second partition when the other of the read and verify operations is in progress.