Flash Memory Spacer Structure for Floating-Gate Coupling Reduction
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Solution Overview
Problem
Conventional flash memory devices face challenges in miniaturization due to increased coupling effects between adjacent floating gates as component sizes shrink, and thicker spacers used to mitigate this hinder further size reduction.
Innovation Solution
A flash memory design featuring a spacer structure with thin and thick spacers, where the thick spacers are located over the thin spacers, forming an air gap with a body portion between the thin spacers and a head portion between the thick spacers, which reduces capacitance between floating gates and improves data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of spacers between word lines is increased to mitigate coupling effects between floating gates, then the coupling effect is reduced, but the component size cannot be miniaturized
Solution Approach 1:
The spacer structure is segmented into two distinct parts: thin spacers at the lower portion and thick spacers at the upper portion. This segmentation allows each part to serve different functions - the thin lower spacers enable miniaturization by reducing overall spacer thickness, while the thick upper spacers mitigate coupling effects between adjacent floating gates, thus resolving the technical contradiction between reliability and miniaturization capability
Solution Approach 2:
Different regions of the spacer structure are given different thickness qualities - the lower portion has thin spacers for miniaturization, while the upper portion has thick spacers for coupling effect mitigation. This local differentiation of quality allows the structure to simultaneously achieve both miniaturization and reliable data retention without requiring uniform thickness throughout
2Productivity
If the spacing of adjacent word lines is reduced to increase component density, then the component density is improved, but the coupling effect between floating gates increases
Solution Approach 1:
The dual-layer spacer structure segments the spacing function between word lines, allowing tight overall spacing for high density while maintaining effective electrical isolation at the critical upper region where floating gates are located, thus enabling high component density without excessive coupling effects
Solution Approach 2:
The thick upper spacers act as intermediary structures between adjacent word lines, providing enhanced electrical isolation that mediates the coupling effect even when word lines are closely spaced, thereby enabling high component density while maintaining reliability
Data Source
AI summary
A flash memory includes multiple gate stacks arranged on a substrate, and a spacer structure. The spacer structure includes multiple thin spacers covering sidewalls of lower portions of the gate stacks and multiple thick spacers covering sidewalls of upper portions of the gate stacks. The thick spacers are located over the respective thin spacers, and the thick spacers are thicker than the thin spacers. The flash memory also includes a dielectric structure disposed on the spacer structure, and an air gap sealed by the dielectric structure and the spacer structure. The air gap includes a body portion between the thin spacers and a head portion between the thick spacers, and the body portion is wider than the head portion.