Flash Memory Stress Area Manufacturing Method
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Solution Overview
Problem
The miniaturization of flash memory devices leads to stress-induced leakage current (SILC) and short channel effects due to reduced oxide layer thickness, limiting device performance and increasing power consumption.
Innovation Solution
A manufacturing method for a flash memory structure with a stress area, involving the formation of L-shaped spacers and a contact etch stop layer between gate structures, using thermal annealing and specific oxide layer deposition to enhance carrier mobility and reduce SILC, by forming a tunneling oxide layer, dielectric layer, and control gate on a silicon substrate, and depositing and etching oxide layers to create stress areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the oxide layer thickness is reduced to increase device density and reduce operating voltage, then device density and speed are improved, but stress-induced leakage current increases and data preservation capability deteriorates
Solution Approach 1:
The patent applies local quality by creating stress areas with different oxide layer thicknesses at specific locations (between adjacent memory cells) while maintaining thin oxide layers in the channel regions. This localized differentiation allows stress-induced leakage current to be suppressed in critical areas without sacrificing the overall device density achieved through thin oxide layers.
Solution Approach 2:
The patent introduces a nitride layer as an intermediary between the thin oxide layer and the silicon substrate in stress areas. This nitride layer acts as a mediator that prevents direct stress transmission that would cause leakage current, while still allowing the thin oxide layer to function for high-density storage in the channel regions.
2Speed
If the oxide layer thickness is reduced to improve device operation speed, then carrier mobility is improved, but stress-induced leakage current increases
Solution Approach 1:
The patent creates spatially differentiated oxide layer structures where thin oxide layers (8nm or below) are maintained in channel regions for high carrier mobility, while thicker oxide layers or nitride-filled stress areas are created in regions between adjacent cells to suppress leakage current. This local quality differentiation resolves the contradiction between speed and harmful leakage.
Solution Approach 2:
The patent segments the oxide layer structure into different regions with different thicknesses and materials - thin oxide in channels for speed, thick oxide or nitride in stress areas for leakage suppression. This segmentation allows each region to be optimized for its specific function without compromise.
3Productivity
If device size is reduced to increase storage density, then device density is improved, but short channel effect becomes more serious
Solution Approach 1:
The patent changes the physical parameters of the oxide layer (thickness, material composition) in specific regions to alter stress distribution characteristics. By creating thicker oxide regions or nitride-filled areas, the stress profile is modified to suppress short channel effects while maintaining the nanoscale dimensions needed for high storage density.
4Reliability
If thermal annealing process is applied to the tunneling oxide layer, then oxide layer quality is improved, but process complexity increases
Solution Approach 1:
The patent optimizes the thermal annealing parameters (temperature range of 750-800°C, time duration of 10-60 minutes) to achieve the desired oxide layer quality improvement with a controlled, standardized process. By defining specific parameter ranges, the process complexity is managed while still achieving significant improvements in oxide layer properties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method improves carrier mobility, reduces stress-induced leakage current, and enhances data preservation by allowing lower read voltage operation while maintaining device performance beyond physical limitations.
Implementation Method 1
the tunneling oxide layer is formed and deposited at 750° C. ̃800° C. and processed with a thermal annealing process at 750° C. ̃800° C.
Implementation Method 2
the second oxide layer becomes an L-shaped spacer aligned towards one another and disposed between the two gate structures to form a first stress area, and a contact etch stop layer on each L-shaped spacer become a second stress area
Data Source
AI summary
In a manufacturing method of a flash memory structure with a stress area, a better stress effect can be achieved by controlling the manufacturing process of a tunneling oxide layer formed in a gate structure and contacted with a silicon substrate, so that an L-shaped spacer (or a first stress area) and a contact etch stop layer (or a second stress area) of each L-shaped spacer are formed between two gate structures and aligned towards each other to enhance the carrier mobility of the gate structure, so as to achieve the effects of improving a read current, obtaining the required read current by using a lower read voltage, reducing the possibility of having a stress-induced leakage current, and enhancing the data preservation of the flash memory.