Flash Memory High-Voltage Switching Circuit Layout Optimization
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Solution Overview
Problem
Conventional high-voltage switching devices in flash memory devices require increased layout area to enhance capacitance, which is inefficient and undesirable.
Innovation Solution
A high-voltage switching unit with a pumping circuit and switching circuit design that includes parallel interconnection areas to increase capacitance without expanding the layout area, utilizing pumping and switching transistors with specific terminal connections and interconnection layouts to enhance voltage levels efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the capacitance of the pumping capacitor is increased to increase the voltage level of the select signal, then the voltage level of the select signal is improved, but the layout area of the switching device increases
Solution Approach 1:
The patent utilizes the vertical dimension by forming a capacitor between the control interconnection area and select interconnection area that extend in parallel. This three-dimensional capacitor structure increases capacitance without requiring additional planar layout area, thereby resolving the contradiction between increasing voltage level and maintaining compact layout.
Solution Approach 2:
The patent merges the capacitor function with the existing interconnection structures (control interconnection area and select interconnection area) by forming a capacitor between them. This integration allows the interconnection areas to serve dual purposes: signal transmission and capacitance storage, thereby increasing capacitance without adding separate components that would expand the layout area.
2Productivity
If the capacitance of the pumping capacitor is increased to efficiently transmit high level voltage, then the high voltage transmission efficiency is improved, but the layout area of the switching device increases
Solution Approach 1:
The patent employs vertical stacking of interconnection areas to create a three-dimensional capacitor structure. This approach increases the effective capacitance for high-voltage pumping while maintaining a compact two-dimensional footprint, thereby improving transmission efficiency without expanding the layout area.
Solution Approach 2:
The control interconnection area and select interconnection area are designed to serve multiple functions: they act as both signal transmission pathways and as plates for forming the pumping capacitor. This multi-functionality increases the capacitance available for high-voltage transmission without requiring additional dedicated capacitor structures that would increase layout area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively increases the voltage level of the select signal while minimizing the layout area, achieving efficient high-voltage transmission without significant area expansion, thereby improving the performance of flash memory devices.
Implementation Method 1
a capacitance is formed between the control interconnection area and the select interconnection area to increase a voltage level of the select signal
Data Source
AI summary
A high-voltage switching device for a flash memory includes at least one pumping transistor which includes one junction terminal and another junction terminal which are commonly connected to a control signal, and a gate terminal connected to a select signal. The high-voltage switching device also includes at least one switching transistor that includes one junction terminal connected to an input signal, another junction terminal connected to an output signal, and a gate terminal connected to the select signal. A layout of the high-voltage switching device includes a pumping active area in which the one junction terminal and the another junction terminal of the pumping transistor are disposed; a control interconnection area in which an interconnection of the control signal is wired; and a select interconnection area in which an interconnection of the select signal is wired.