Flash Memory Array Top Gate Control for Power and Disturbance Reduction

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Solution Overview

Problem

Conventional flash memory systems face challenges in efficiently managing high voltage signals for erase, programming, and read operations, particularly in multilevel memory cells, which can lead to power consumption issues and disturbances during programming and reading.

Innovation Solution

A flash memory array system with multilevel memory cells featuring a top gate structure that includes a floating gate, a select gate, and a top coupling gate, allowing for efficient Fowler-Nordheim tunneling for erase and source side injection programming, reducing power consumption and minimizing disturbances by dynamically controlling the top gate voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If high voltage signals are applied to flash memory cells for erase and programming operations, then programming efficiency is improved, but power consumption increases

Engineering Contradiction:

Improveprogramming efficiencyVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The gate structure is segmented into multiple independent gates (select gate, top gate, floating gate) that can be controlled separately. This allows selective application of high voltage only to specific gates during specific operations, rather than applying high voltage to all gates simultaneously, thereby reducing overall power consumption while maintaining programming efficiency.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic control of the top gate voltage through a control circuit that adjusts the top gate signal based on operation type (erase, program, read). During read operations, the top gate is disabled or held at low voltage, while during programming and erasing, high voltage is applied only when needed. This dynamic voltage adjustment reduces power consumption during idle and read states while maintaining high programming efficiency when required.

Inventive Principle:

Principle #15Dynamics

2Speed

If high voltage signals are applied during programming operations, then programming speed is improved, but disturbances to other memory cells increase

Engineering Contradiction:

Improveprogramming speedVSAvoiddisturbances during programming

Core Design Contradiction:

SpeedVSObject-affected harmful factors

Solution Approach 1:

The patent applies high voltage locally and selectively to only the selected memory cell being programmed, while other memory cells remain at low voltage. The control circuit enables precise selection and activation of specific word lines and bit lines, ensuring that high voltage programming signals affect only the targeted cell and not neighboring cells, thus eliminating programming disturbances while maintaining high programming speed.

Inventive Principle:

Principle #3Local quality

3Reliability

If top gate is always enabled for multilevel memory cell operations, then memory cell reliability is improved, but power consumption increases

Engineering Contradiction:

Improvememory cell reliabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The control circuit implements periodic or conditional enabling of the top gate based on the specific operation being performed. The top gate is enabled only during erase and programming operations where it is needed for reliable operation, and is disabled during read operations or idle states. This periodic activation maintains memory cell reliability when required while significantly reducing power consumption during non-critical operations.

Inventive Principle:

Principle #19Periodic action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The system achieves low voltage and low power performance with high programming efficiency, reducing power consumption and minimizing disturbances during operations, enabling efficient programming and reading of multilevel memory cells.

Implementation Method 1

allowing for efficient Fowler-Nordheim tunneling for erase

Methodology Applied

Scientific EffectFowler-Nordheim tunneling:

Implementation Method 2

source side injection programming

Methodology Applied

Scientific EffectSource side injection:

Data Source

PatentUS7567458B2Flash memory array having control/decode circuitry for disabling top gates of defective memory cells

Publication Date: 2009.07.28 SILICON STORAGE TECHNOLOGY INC

AI summary

A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.