Read-Only Memories TRIZ Cases

A 3D NAND flash memory erase method applies specific low voltages to induce gate-induced drain leakage.

Shift registers spatially separate memory matrices in a split memory bank, reducing footprint and routing complexity for larger storage capacity.

Segmenting NAND flash blocks into independently erasable pages prevents adjacent cell interference during partial data corrections.

A sense amplifier latch circuit stores data using internal node signals to simplify timing management.

A sensing circuit uses an operational amplifier to control a load PMOS gate voltage, stabilizing output resistance.

SRAM retention mode uses error correction codes to maintain data accuracy during low voltage operation.

A resistive memory cell switches between resistance and charge storage modes to consolidate volatile and non-volatile functions into a single component.

Dynamic top gate control reduces power consumption and minimizes disturbances during multilevel memory cell operations.

A NAND flash memory test latch circuit distributes pre-loaded data patterns to multiple internal data latches via a switching controller.

Reprogramming failed memory cells with reinforced pulses during idle states resolves programming reliability issues caused by pulse strength variations.

A nonvolatile memory circuit uses a shift register to activate latch circuits, resolving slow boot-up repair data transmission.

A vertical NAND string uses a self-aligned select gate to couple ends concurrently, reducing effective cell size.

Two-phase cascode biasing isolates the gate terminal to boost voltage, balancing fast precharge speed with low static current consumption.

A dual-purpose charge pump recovers electric charge from capacitive power distribution networks during sleep modes.

Time domain transformation of electrical variables enables reliable blank state detection in non-volatile memory cells.

A word line test circuit detects defects using a comparison signal and reference clock counts.

A non-volatile semiconductor memory device performs segmented verify operations to control threshold voltage states in adjacent memory cells.

Adjustable LDO resistance limits peak current during memory power-up, preventing damage from excessive inrush while maintaining stable voltage supply.

Applying precharge voltage to string select lines reduces hole trapping during erase operations, preventing threshold voltage reduction in transistors.

A memory apparatus applies erase voltage pulses to channels in memory holes while verifying threshold voltages against target and high levels.

Incremental step pulse programming trims 3D NAND control transistors to reduce leakage while maintaining fast programming speed.

A flash memory device uses a dedicated set-up data region to store initialization information for rapid system startup.

Segmented spare memory arrays paired with dedicated reference cells enable additional data programming in nonvolatile storage.

A flash memory device incorporates ROM-enable portions to designate sectors as read-only or programmable.

Coupling information pads enable semiconductor chips to selectively store unique setting information while sharing command and address channels.

A voltage regulator output driver uses a clamp circuit to limit gate-to-source voltage on thin oxide transistors.

A nonvolatile semiconductor memory device applies differentiated pass voltages to adjacent and distant nonselective word lines during programming operations.

A two-stage in-memory search method applies distinct voltage levels to memory cells and reads resulting currents to determine data states.

A nonvolatile memory programming method adjusts voltage margins between program states based on detected logic state presence.

Terminating verify operations upon suspend requests reduces threshold voltage distribution deterioration and maintains programming speed.

Signal pulses drive memory cells through snapback events to adjust resistance states, reducing energy consumption during programming operations.

Connection transistors in the semiconductor substrate replace lowermost layer select gates to improve manufacturing and operation controllability.

A page buffer detects defects by applying a test voltage to a sensing node and measuring leakage current, resolving reliability versus complexity trade-offs.

A memory device adjusts read signal voltage levels based on dummy read operations to compensate for cell deterioration.

A flash memory controller calculates remaining operation time to selectively suspend lower priority tasks.

Segments memory cells to apply distinct erase pulses, preventing over-erasure and ensuring uniform threshold voltages.

Redundant thermometer circuits powered by separate voltage sources detect out-of-range temperatures to prevent data corruption.

A semiconductor memory device uses a delay estimation mechanism to adjust output timing in response to external control signals.

Tracking bit flip ratios in NAND flash memory enables dynamic read voltage adjustment, reducing latency from threshold drift retries.

Adjusting bit line voltages across a memory plane compensates for time constant variations along the word line, reducing required programming pulses.

Dynamic switch control reduces parasitic capacitance from unselected memories, maintaining reference channel values to prevent signal overshoot and undershoot.

Buffering program commands and data allows the control circuit to generate enable signals automatically, reducing overall program time in phase change memory.

A secondary memory device integrates a detachable battery module with substrate control circuitry to supply backup power during external source failures.

A non-volatile memory device adjusts erase voltages using Gate Induced Drain Leakage to manage cell subsets.

Segmenting LCR issuance with SDRAM active periods prevents output interruptions, enhancing access speed and bus utilization efficiency.

A memory device with an internal controller locks access to sensitive data upon detecting locking content.

Progressive voltage pulses program multi-level cell NAND memory states sequentially, reducing power consumption while maintaining high storage density.

A read sensing circuit charges a data line with cell current to monitor storage states in one time programmable memory arrays.