LDO Peak Current Control for Memory Power-Up
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Solution Overview
Problem
During the power-up of memory devices, the connection of a capacitive load to the power supply results in a peak current, which can be excessive due to increased die size and memory cell density, posing a challenge for effective peak current control.
Innovation Solution
The implementation of a low-dropout regulator (LDO) with an error amplifier and transmission gates to control the peak current by setting the equivalent resistance, ensuring a regulated voltage and sufficient current for the memory device during power-up.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If die size and memory cell density are increased, then memory capacity is improved, but peak current during power-up increases excessively
Solution Approach 1:
The patent applies preliminary action by enabling the LDO regulator before the capacitive load is fully connected during power-up. The regulator is activated in advance to establish controlled current pathways, preventing the sudden inrush current that would otherwise occur when the capacitive load connects directly to the power supply. This timing control resolves the contradiction by preparing the current control mechanism before the high-current event occurs.
Solution Approach 2:
The LDO regulator serves as an intermediary component between the power supply and the capacitive load. Instead of allowing direct connection that causes excessive peak current, the regulator mediates the power delivery by controlling the current flow through its resistance characteristics. This intermediary device enables high memory capacity devices to power up without excessive peak current by inserting a controlled impedance element in the power path.
2Reliability
If peak current is limited during power-up, then device safety is improved, but current supply to capacitive load is reduced
Solution Approach 1:
The patent applies dynamics by making the LDO regulator's resistance characteristic adjustable rather than fixed. The regulator transitions from a high-resistance state during initial power-up (limiting peak current) to a lower-resistance state as power-up progresses (increasing current supply). This dynamic adjustment resolves the contradiction by adapting the current limitation level to the instantaneous needs of the capacitive load during the power-up sequence.
Solution Approach 2:
The patent implements periodic action through the staged power-up sequence where the LDO regulator operates in different modes at different times. Initially, the regulator provides strong current limiting to protect the device; then, as power-up progresses and the capacitive load becomes fully connected, the regulator transitions to providing sufficient current for normal operation. This time-based mode switching resolves the contradiction between peak current limitation and current supply requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively limits the peak current during power-up, preventing potential damage to the memory device and ensuring stable operation by managing the current supply through the LDO's resistance control.
Implementation Method 1
controlling the peak current by setting an equivalent resistance of the LDO
Data Source
AI summary
A low-dropout regulator includes an error amplifier to provide a control signal, a first transistor, and a second transistor. The first transistor receives the control signal and has a source-drain path electrically coupled between a supply voltage node and a load, the first transistor to power the load in response to a voltage on the supply voltage node rising above an absolute value of a threshold voltage of the first transistor. The second transistor has a source-drain path electrically coupled between the supply voltage node and the load, the second transistor to receive the control signal in response to the voltage on the supply voltage node rising above a particular voltage.