String-Based Erase Inhibit for Gate-Induced Drain Leakage
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Solution Overview
Problem
Existing non-volatile memory technologies face issues with over-erasing during the erase operation, leading to degradation of memory cells due to excessive hole accumulation in the tunneling path, which is not effectively addressed by current erase-verify methods.
Innovation Solution
A memory apparatus and method that apply a first erase voltage in a first loop, verify the threshold voltage using target and high erase verify levels, and slow down the erase process in a second loop for cells with threshold voltages between these levels to prevent over-erasing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a standard erase voltage is applied continuously to erase memory cells, then the erase operation completes faster, but over-erasing occurs causing memory cell degradation due to excessive hole accumulation
Solution Approach 1:
The erase operation is divided into multiple loops with periodic verify operations. The controller applies erase voltage in pulses separated by verify intervals, switching between erase mode and verify mode periodically. This prevents continuous exposure to high voltage that causes over-erasing, while still achieving complete erasure through repeated cycles.
Solution Approach 2:
The verify operation provides feedback to the controller about the current state of memory cells. Based on this feedback (whether cells have reached the erased state), the controller adjusts subsequent erase operations. Cells that are already erased are inhibited from further erasure, while cells that need erasing continue to receive erase voltage, preventing over-erasing of completed cells.
2Reliability
If the erase voltage is reduced to prevent over-erasing, then memory cell degradation is reduced, but the erase operation takes longer to complete
Solution Approach 1:
The erase voltage is dynamically adjusted based on the real-time state of memory cells. In the first loop, a higher erase voltage is applied to quickly erase cells that need it. In subsequent loops, the voltage is adjusted based on verify results, applying voltage only to cells that haven't reached the erased state. This dynamic adjustment optimizes both speed and reliability.
Solution Approach 2:
The erase operation is segmented into multiple loops, with each loop targeting specific subsets of memory cells based on their erasure status. The first loop erases all selected cells, and subsequent loops selectively erase only those cells that haven't reached the target state, dividing the overall task into manageable segments that optimize both speed and cell protection.
3Measurement precision
If multiple verify levels are used to check threshold voltage, then erasure accuracy is improved, but the verify operation becomes more complex and time-consuming
Solution Approach 1:
Instead of using multiple verify levels for all cells, the patent uses a tiered approach: a first verify level (target erase verify level) is used for all cells to determine if erasure is complete, and a second verify level (high erase verify level) is used only for cells that fail the first verify. This partial application of excessive verification reduces overall complexity while maintaining precision where needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents over-erasing, reducing memory cell degradation and improving the reliability and efficiency of the erase operation.
Implementation Method 1
A charge-trapping material can be arranged vertically in a three-dimensional (3D) stacked memory structure, or horizontally in a two-dimensional (2D) memory structure
Implementation Method 2
The control means verifies the threshold voltage of the memory cells being erased using a target erase verify level voltage and at least one high erase verify level voltage higher than the target erase verify level voltage
Data Source
AI summary
A memory apparatus includes memory cells configured to store a threshold voltage and disposed in memory holes each defining a channel. The memory apparatus also includes a control means configured to apply a first erase voltage to the channel of each of the memory holes including the memory cells in a first loop of an erase operation. The control means verifies the threshold voltage of the memory cells being erased using a target erase verify level voltage and at least one high erase verify level voltage higher than the target erase verify level voltage. The control means slows erasing of ones of the memory cells in a second loop of the erase operation in response to the threshold voltage of the ones of the memory cells being erased being greater than the target erase verify level voltage and less than the at least one high erase verify level voltage.