Synchronous Memory Controller Command Segmentation
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Solution Overview
Problem
In synchronous memory systems, the issuance of the LCR command for compatibility with SDRAM and flash memory can interrupt data output from SDRAM, causing delays and reducing memory access efficiency due to the need for additional clock cycles and special command processing.
Innovation Solution
A synchronous memory system design where a synchronous memory controller processes unique commands for the flash memory within the same data bus as SDRAM, eliminating the need for a special cycle for processing these commands and avoiding interruptions to SDRAM data output by synchronizing command processing with existing clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the LCR command is issued prior to the ACTIVE command to ensure compatibility with SDRAM and flash memory, then compatibility is maintained, but the data output of SDRAM is interrupted and memory access operations are delayed
Solution Approach 1:
The LCR command is issued in advance during the ACTIVE command execution period of SDRAM, before the flash memory needs to access data. This preliminary action prepares the flash memory's command decoding circuitry and voltage generation circuitry without interrupting SDRAM operations, thereby maintaining compatibility while avoiding access delays
Solution Approach 2:
The patent enables continuous data output from SDRAM by overlapping the LCR command issuance with the ACTIVE command execution period. The flash memory's command decoding circuitry processes the LCR command during idle periods within the SDRAM active cycle, ensuring that SDRAM data output continues uninterrupted while flash memory is prepared for subsequent operations
2Productivity
If three continuous commands are issued in the LCR-ACTIVE-WRITE command cycle to perform ERASE operation, then flash memory operations are completed, but the chance of interrupting SDRAM data output increases
Solution Approach 1:
The patent segments the command issuance process by dividing the three continuous commands (LCR, ACTIVE, WRITE) into separate execution phases. The LCR command is issued during the ACTIVE command execution period of SDRAM, the ACTIVE command is issued after LCR completion, and the WRITE command is issued subsequently. This segmentation prevents simultaneous command conflicts that would interrupt SDRAM data output while still completing all necessary flash memory operations
Solution Approach 2:
The patent introduces dynamic timing control where the issuance timing of each command in the sequence is adjusted based on the execution status of SDRAM operations. The LCR command timing is dynamically set to overlap with SDRAM ACTIVE command execution, while subsequent commands are timed to avoid conflicts with SDRAM data output periods, thereby maintaining reliability while achieving productivity goals
Data Source
AI summary
Systems, methods, and circuits for command control for synchronous memory device are disclosed. In one embodiment, a memory device comprises a first synchronous memory controlled by a second group of commands which includes a first command receiving section for receiving a first group of commands, and a second command receiving section for receiving a command that is unique to the first synchronous memory and different from the first group of commands during execution of the first group of commands received by the first command receiving section. The synchronous memory further comprises a second synchronous memory controlled by the first group of commands, where the first synchronous memory and the second synchronous memory are coupled to a same data bus, and where the second group of commands is different from the first group of commands.