Nonvolatile Memory Connection Transistors for Select Gate Controllability

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Solution Overview

Problem

Current nonvolatile semiconductor memory devices face challenges in manufacturing and operation controllability, particularly in the I-shaped BiCS memory, where select gates at the lowermost layer have poor controllability and it is difficult to remove insulating layers formed at the bottom surfaces of memory holes.

Innovation Solution

The configuration includes connection transistors with insulating layers formed at the bottom surfaces of memory holes, semiconductor pillars, and a semiconductor substrate, where the current paths of connection transistors are connected in series, eliminating the need for select gates at the lowermost layer and allowing for improved manufacturing and operation controllability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If select gates are placed at the lowermost layer of I-shaped BiCS memory, then memory string selection is enabled, but manufacturing precision and operation controllability deteriorate

Engineering Contradiction:
Improveselect gate controllabilityVSAvoidinsulating layer removal difficulty
Core Design Contradiction:
Ease of operationVSManufacturing precision

Solution Approach 1:

The patent extracts the select gate function from the lowermost layer of the memory structure. Instead of placing select gates at the bottom of memory holes, the invention uses connection transistors formed in the semiconductor substrate to perform the selection function, thereby eliminating the need to form and remove insulating layers at the lowermost layer, which resolves the manufacturing precision issue while maintaining operational controllability

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent moves the select gate function from the vertical dimension (lowermost layer of memory holes) to the horizontal dimension (connection transistors in the substrate plane). This dimensional shift allows selection to be performed through connection transistors that connect memory strings to bit lines, avoiding the need for lowermost layer select gates and their associated insulating layer removal processes

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If connection transistors are used instead of lowermost layer select gates, then manufacturing and operation controllability improve, but device complexity increases

Engineering Contradiction:
Improvemanufacturing controllabilityVSAvoidtransistor structure complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The connection transistors perform multiple functions: they serve as selection switches for memory strings, act as access transistors to bit lines, and provide current path control. By making the connection transistors multi-functional, the patent eliminates the need for separate lowermost layer select gates, thereby reducing manufacturing steps and improving controllability without adding significant device complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the functions of connection transistors and select gates into a single structure. The connection transistors simultaneously perform the roles of accessing memory strings and selecting them for operation, combining what would traditionally be separate components into one integrated element, thus simplifying the overall device structure

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9218882B2Nonvolatile semiconductor memory device
Publication Date: 2015.12.22 KIOXIA CORP
  • US9218882B2 patent drawing
  • US9218882B2 patent drawing
  • US9218882B2 patent drawing

AI summary

A nonvolatile semiconductor memory device includes a first memory string including memory cell transistors and a first select transistor that are connected in series, a second memory string including memory cell transistors and a second select transistor that are connected in series, a bit line that is electrically connected to a first end of the first memory string and a first end of the second memory string, a first transistor having a gate that is connected to a second end of the first memory string, a source line that is electrically connected to a first end of the first transistor, and a second transistor having a gate that is connected to a second end of the second memory string, a first end that is electrically connected to a second end of the first transistor, and a second end that is electrically connected to the bit line.