MLC NAND Programming via Progressive Voltage Pulses
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Solution Overview
Problem
Multi-state programming operations in non-volatile memory structures, such as MLC and TLC, face challenges with slower programming speeds and increased power consumption due to the need for precise voltage control across multiple threshold voltage ranges, which limits their performance compared to single-level cell (SLC) memory.
Innovation Solution
A method for programming MLC type memory cells using distinct programming voltages in multiple pulses, where the magnitude of each voltage is progressively greater, allowing for the simultaneous or sequential programming of multiple states within a single or few program pulses, thereby optimizing programming speed and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-state programming operations are used to increase storage density, then storage capacity is improved, but programming speed deteriorates
Solution Approach 1:
The programming operation is segmented into multiple distinct program pulses, each with progressively greater magnitude. The first program pulse programs memory cells to a first programmable state, the second program pulse programs to a second programmable state, and the third program pulse programs to a third programmable state. This segmentation allows simultaneous or sequential programming of multiple states without requiring sequential operations, thereby improving programming speed while maintaining multi-state storage capability.
Solution Approach 2:
The patent employs periodic program pulses with increasing magnitude to program multiple states. By applying a series of program pulses at different voltage levels in sequence, the memory cells can be programmed to different threshold voltage ranges corresponding to different data states. This periodic action with varying parameters enables efficient multi-state programming while maintaining high programming speed.
2Quantity of substance
If multi-state programming operations are used to increase storage density, then storage capacity is improved, but power consumption increases
Solution Approach 1:
The patent merges multiple programming operations into a single integrated process. By applying multiple program pulses with progressively greater magnitude to the same memory cell population, the system programs multiple states (first, second, and third programmable states) in what is described as a single programming operation. This consolidation reduces the total number of separate programming cycles required, thereby reducing overall power consumption while achieving multi-state storage.
Solution Approach 2:
The first program pulse with lower magnitude serves as a preliminary action that programs memory cells to an intermediate state. This preliminary programming prepares the memory cells for subsequent programming to higher states by the second and third program pulses. By establishing an intermediate state first, the overall programming process becomes more efficient and consumes less power than attempting to program to the final state directly.
3Manufacturing precision
If precise voltage control is applied across multiple threshold voltage ranges, then programming accuracy is improved, but programming complexity increases
Solution Approach 1:
The patent employs parameter changes by varying the magnitude of program pulses across three distinct levels. The first program pulse uses a first magnitude, the second program pulse uses a second magnitude greater than the first, and the third program pulse uses a third magnitude greater than the second. These parameter changes enable precise control over the threshold voltage ranges of memory cells, allowing accurate programming to different states while maintaining relatively simple control logic.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the programming speed and reduces power consumption by consolidating program pulses, improving the efficiency of multi-state memory operations while maintaining or exceeding the performance of SLC memory.
Implementation Method 1
each memory cell is comprised of a floating gate that is positioned above and isolated from a channel region of a semiconductor substrate, wherein the floating gate is positioned between the source and drain regions. Also, a control gate is provided over and isolated from the floating gate, wherein the threshold voltage (Vth) of the resulting transistor is then controlled by and dependent upon an amount of charge that is retained on the floating gate.
Implementation Method 2
the threshold voltage (Vth) of the resulting transistor is then controlled by and dependent upon an amount of charge that is retained on the floating gate
Data Source
AI summary
A method for programming a memory array of a non-volatile memory structure, wherein the memory array comprises a population of MLC NAND-type memory cells, and the method comprises: (1) in a first program pulse, programming selected memory cells according to a first programmable state and a second programmable state, and (2) in a second program pulse, programming the selected memory cells according to a third programmable state.