Split Memory Bank for Integrated Printheads
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Solution Overview
Problem
As memory bits used in integrated printheads increase, the footprint of the Erasable Programmable Read-Only Memory (EPROM) also grows, with memory bits doubling every year or two, leading to space constraints and increased area occupation.
Innovation Solution
A split memory bank design is implemented, where a shift register physically separates memory matrices, reducing the number of electrical connections and thus the footprint, with a 25% reduction in routing lines and 14% reduction in width, allowing for more efficient use of space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory bits are increased to meet growing storage requirements, then data storage capacity is improved, but the footprint and area occupied by the EPROM increases
Solution Approach 1:
The memory bank is divided into multiple memory matrices (first matrix, second matrix, third matrix, fourth matrix) that are spatially separated by shift registers. This segmentation allows the memory to be organized in a distributed layout rather than a single dense block, reducing the overall footprint while maintaining total storage capacity.
Solution Approach 2:
The patent transitions from a two-dimensional dense array layout to a more distributed spatial arrangement where memory matrices are separated by shift registers. This dimensional reorganization allows better utilization of available space and reduces the bounding box footprint of the memory bank.
2Quantity of substance
If more memory matrices are added to increase storage capacity, then data storage capacity is improved, but the number of electrical connections and routing complexity increases
Solution Approach 1:
Shift registers are introduced as intermediary components between memory matrices. These shift registers serve as buffer and control elements that simplify the connection architecture, reducing the number of direct electrical connections needed between memory matrices and control logic, thereby reducing routing complexity.
Solution Approach 2:
The shift registers perform multiple functions: they act as buffers between memory matrices, provide control signal distribution, and enable sequential access to different memory matrices. This multi-functionality reduces the need for separate dedicated control circuits for each memory matrix, simplifying the overall routing architecture.
Data Source
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AI summary
A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.