NAND Flash Memory Cell Verify Operation for Threshold Voltage Distribution
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Solution Overview
Problem
The increasing miniaturization of NAND flash memories leads to coupling noise and cell-to-cell interference issues, causing broadening of threshold voltage distributions during data write operations, which affects the accuracy of program and verify operations in non-volatile semiconductor memory devices.
Innovation Solution
The implementation of a non-volatile semiconductor memory device with a data write portion that includes two verify operations in specific write loops, where the first verify operation is performed with precharged bit-lines and the second without precharging, to adjust and verify the threshold voltage of memory cells, thereby reducing the impact of coupling noise and cell interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the NAND flash memory is miniaturized to increase integration capacity, then the unit cell area is reduced and larger capacity is achieved, but coupling noise between adjacent memory cells increases causing threshold voltage distribution broadening
Solution Approach 1:
The verify operation is segmented into two distinct modes: first verify operation with precharged bit-lines and second verify operation without precharging. This segmentation allows separate verification of memory cells at different voltage states, preventing coupling noise from broadening threshold voltage distribution while maintaining high capacity
Solution Approach 2:
The bit-line is precharged to a specific voltage level before the first verify operation to establish a reference state that compensates for coupling noise effects. This preliminary action ensures accurate threshold voltage measurement despite the miniaturized cell structure
2Measurement precision
If the verify operation is performed without precharging bit-lines, then the threshold voltage verification accuracy is improved, but the write operation time increases
Solution Approach 1:
The verify operation alternates between two periodic modes: first verify with precharged bit-lines for fast initial verification, and second verify without precharging for accurate final verification. This periodic alternation balances speed and accuracy requirements
Solution Approach 2:
The bit-line voltage parameter is dynamically changed between two states: precharged voltage during first verify operation for speed, and non-precharged state during second verify operation for accuracy. This parameter change enables the system to achieve both fast and accurate verification
3Productivity
If the program operation accumulates charges rapidly in the floating gate, then the write speed is improved, but the threshold voltage distribution broadens due to cell-to-cell interference
Solution Approach 1:
The dual verify operation provides feedback control for the program operation: the first verify operation gives initial feedback for fast programming, and the second verify operation provides corrective feedback to narrow threshold voltage distribution. This feedback mechanism maintains write speed while preventing distribution broadening
Data Source
AI summary
A non-volatile semiconductor memory device according to an embodiment includes a data write portion, the data write portion includes, in a write loop, a first operation mode of sequentially performing a program operation and a first verify operation, and a second operation mode of sequentially performing the program operation, the first verify operation, and a second verify operation, and the data write portion includes, in the first verify operation, precharging a bit-line connected to the first memory cell and a bit-line connected to a second memory cell adjacent to the first memory cell and verifying data of the first memory cell, then in the second verify operation, when the write to the second memory cell is completed, without precharging the bit-line connected to the second memory cell, precharging the bit-line connected to the first memory cell and verifying data of the first memory cell.