3D NAND Flash Memory Erase Method for PUF Data Stability
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Solution Overview
Problem
The physical unclonable function (PUF) data in 3D flash memory becomes unstable due to the program erase cycle, affecting the reliability of identity verification and security applications.
Innovation Solution
A memory erase method that applies specific erase voltages to memory cell strings to induce gate-induced drain leakage (GIDL) erasing, resulting in random threshold voltage distributions and stable PUF data, allowing for the classification of memory cells into type-1 and type-2 erase bits, ensuring consistent PUF data across pages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional erase methods are used in flash memory, then the memory cells can be erased, but the PUF data becomes unstable after large amounts of programming/erasing cycles
Solution Approach 1:
The patent changes the erase voltage parameter to a specific range (2.0V-4.0V) that is lower than conventional erase voltages. This parameter change enables gentle erasing that does not significantly alter the physical characteristics of memory cells, thereby maintaining stable PUF data even after numerous program/erase cycles
Solution Approach 2:
The patent applies partial erasing action by using reduced erase voltages that do not completely clear the memory cells. This partial action is sufficient to generate the required threshold voltage distributions for PUF while avoiding the excessive erasing that would degrade cell physical characteristics and stabilize PUF data over time
2Productivity
If high erase voltages are applied to erase memory cells, then the erasing operation is effective, but the physical characteristics of memory cells change making PUF data unstable
Solution Approach 1:
The patent fundamentally changes the erase voltage parameter from conventional high voltages to a specific low voltage range (2.0V-4.0V). This parameter change enables effective erasing for PUF generation while preserving the physical characteristics of memory cells, thus maintaining PUF data stability
Solution Approach 2:
The patent converts the typically harmful effect of low erase voltages (ineffective erasing) into a beneficial effect by precisely controlling the voltage to generate the desired threshold voltage distributions for PUF while avoiding the harmful physical changes that occur at high voltages
3Ease of operation
If memory cells are erased using conventional methods, then the erase operation completes, but different memory cell strings have different threshold voltage distributions reducing PUF reliability
Solution Approach 1:
The patent applies a unified low voltage parameter (2.0V-4.0V) across all memory cell strings during the erase operation. This consistent parameter application ensures that all memory cell strings develop similar threshold voltage distributions, thereby improving PUF data consistency and reliability
Solution Approach 2:
The patent creates equipotentiality in the erase process by applying the same low voltage condition to all memory cell strings simultaneously. This ensures uniform threshold voltage distribution across all strings, eliminating the variability that would otherwise reduce PUF reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method stabilizes PUF data by ensuring all memory cells in a string have the same threshold voltage distribution, reducing the impact of program erase cycles and enabling reliable data generation, even when the programming-erasing count exceeds the wear threshold, by switching to a different page for data generation.
Implementation Method 1
applies specific erase voltages to memory cell strings to induce gate-induced drain leakage (GIDL) erasing
Data Source
AI summary
A memory erase method for a memory device and a memory device therefore are provided. The memory device is a 3D NAND flash with high capacity and high performance. The memory erase method includes following steps: providing a memory block, wherein the memory block comprises memory cell strings, the memory cell strings include memory cells, string selection transistors and ground selection transistors; respectively applying corresponding erase voltages to corresponding word lines, a common source line, a corresponding bit line, the string selection transistor and the ground selection transistor of each of the memory cell strings. The voltage difference between a bit line erase voltage and a string selection line erase voltage or the voltage difference between the common source line erase voltage and the ground selection line erase voltage is less than or equal to a predetermined voltage difference, and the memory cells of the memory cell strings randomly classified as a type-1 erase bit or a type-2 erase bit.