OTP Memory Read Sensing Circuit for State Recognition

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Solution Overview

Problem

Existing one-time programmable (OTP) non-volatile memory technologies face challenges in accurately recognizing the storage states of OTP memory cells due to different impedance states, requiring distinct read sensing circuits for anti-fuse and fuse type cells, which complicates the read sensing process.

Innovation Solution

A read sensing method where the bit line corresponding to the selected OTP memory cell is continuously connected with a data line, allowing the cell current to charge the data line, enabling continuous monitoring and recognition of the storage state based on output signals, utilizing a memory array with a controlling circuit, precharge circuit, column selector, reset circuit, and sense amplifier.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If different read sensing circuits are used for anti-fuse and fuse type OTP memory cells, then the storage states can be accurately recognized, but the device complexity increases

Engineering Contradiction:
Improvestorage state recognition accuracyVSAvoidread sensing circuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent employs a single read sensing circuit that can sense both anti-fuse type and fuse type OTP memory cells. The circuit achieves this universality by dynamically adjusting its sensing parameters and signal levels based on the cell type being read, eliminating the need for separate dedicated circuits for each memory cell type while maintaining accurate state recognition

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The read sensing circuit changes its operating parameters such as reference voltage levels, sensing current, and decision thresholds depending on whether it is reading an anti-fuse type or fuse type memory cell. This parameter adaptation allows the same physical circuit to accurately sense different impedance states corresponding to different memory cell types

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If a single read sensing circuit is used for both anti-fuse and fuse type OTP memory cells, then the device complexity is reduced, but the measurement precision may deteriorate

Engineering Contradiction:
Improveread sensing circuit complexityVSAvoidstorage state recognition accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The read sensing circuit incorporates dynamic control mechanisms that adjust its sensing characteristics in real-time based on the type of memory cell being accessed. The circuit can switch between different sensing modes and reference levels, making it adaptable to the specific impedance characteristics of either anti-fuse or fuse type cells, thereby maintaining high measurement precision despite using a single unified circuit

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for accurate recognition of the storage state of OTP memory cells by continuously charging the data line with cell current, simplifying the read sensing process and improving the reliability of state determination.

Implementation Method 1

the cell current outputted from the selected OTP memory cell continuously charges the data line, so that a voltage level of the data line is changed

Methodology Applied
Scientific EffectElectrical current charging: Capacitance

Data Source

PatentUS9653177B1One time programmable non-volatile memory and read sensing method thereof
Publication Date: 2017.05.16 EMEMORY TECH INC
  • US9653177B1 patent drawing
  • US9653177B1 patent drawing
  • US9653177B1 patent drawing

AI summary

A read sensing method for an OTP non-volatile memory is provided. The memory array is connected with plural bit line pairs. Firstly, the plural bit line pairs are precharged to a precharge voltage. Then, a selected memory cell connected with a specific bit line pair is determined. Then, two bit lines of the specific bit line pair are respectively connected with the data line and the reference line and are discharged to a reset voltage. After a first cell current and a second cell current from the specific bit line pair are received, a first voltage level of the data line and a second voltage level of the reference line are gradually changed from the reset voltage. According to a result of comparing the first voltage level and the second voltage level, an output signal is generated.