SRAM Retention Mode Error Correction via ECC and Voltage Control
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Solution Overview
Problem
SRAM circuits face challenges in reducing power consumption during retention mode without compromising data integrity, as lowering the supply voltage can cause transistors to flip states, leading to data loss and errors.
Innovation Solution
Implementing error correction capabilities and adjusting transistor threshold voltages to maintain data integrity by using ECC codes and determining the minimum retention voltage through testing, allowing for reduced power consumption while ensuring data accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If the supply voltage is lowered during retention mode, then power consumption is reduced, but data integrity deteriorates due to transistor state flipping
Solution Approach 1:
The patent applies preliminary action by performing error correction coding (ECC) on data before writing it to the SRAM array. This allows the system to tolerate certain levels of data corruption during low-voltage retention mode without losing information, as the ECC codes can reconstruct the original data even if some bits flip due to insufficient voltage.
Solution Approach 2:
The patent changes the voltage parameter dynamically by implementing multiple retention voltage levels (first retention voltage and second retention voltage). The system can switch between these voltage levels based on operational requirements, allowing lower voltage (and thus lower power consumption) when full data integrity is not critical, while maintaining the ability to use higher voltage when data integrity is paramount.
2Duration of action of moving object
If the supply voltage is lowered during retention mode, then battery life is extended, but error rates increase due to insufficient voltage for stable transistor operation
Solution Approach 1:
By pre-computing and storing ECC codes with the data before entering retention mode, the system enables lower voltage operation during retention without sacrificing data accuracy. The ECC protection is already in place, so the system can afford to run at lower voltages that would otherwise cause errors, thereby extending battery life while maintaining data integrity through the predetermined error correction capability.
3Reliability
If error correction is implemented, then data integrity is improved, but device complexity increases due to additional ECC circuitry and testing requirements
Solution Approach 1:
The patent segments the SRAM array into multiple blocks, with at least one block configured with ECC capability. This selective segmentation allows error correction to be applied only where needed, rather than throughout the entire memory array, thereby reducing the overall complexity increase while still providing data integrity protection for critical data storage areas.
Data Source
AI summary
A method for storing information in SRAM bit cell arrays provides for lowering voltage supplied to the SRAM bit cell arrays, with voltage lowering controlled by a connected voltage control circuit. Writing, reading, and correcting information storable in the SRAM bit cell arrays is accomplished using an error correcting code (ECC) block connected to at least some of the SRAM bit cell arrays. The ECC block is configurable to repair stored information.