Nonvolatile Memory Switches for Parasitic Capacitance Reduction
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Solution Overview
Problem
In multi-stack chip packages of nonvolatile memory devices, parasitic capacitance from unselected memories can lead to reliability issues due to resistance and signal integrity problems during read, write, or copy-back operations, causing overshoot and undershoot, which necessitates adjusting the channel capacitance to a reference value.
Innovation Solution
The implementation of a nonvolatile memory device with a switch-controlled data input/output circuit that adjusts the switching voltage based on measured capacitance and operational conditions, such as use time and program/erase cycles, to manage the capacitance of unselected memories, ensuring the channel capacitance matches a reference value, thereby improving signal integrity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple nonvolatile memories are connected through the same channel to achieve high-capacity and high-speed input/output, then storage capacity and I/O speed are improved, but parasitic capacitance increases causing reliability degradation and signal integrity problems
Solution Approach 1:
The patent implements dynamic control of data input/output switches by selectively turning them on or off based on whether the corresponding nonvolatile memory is selected for operation. This dynamic switching mechanism adjusts the electrical characteristics of the channel in real-time, reducing parasitic capacitance when memories are not actively being accessed, thereby maintaining signal integrity while enabling multi-memory connectivity for high capacity and speed
2Reliability
If the driving force is increased to reduce parasitic capacitance effects, then signal integrity is improved, but overshoot and undershoot problems occur
Solution Approach 1:
The patent changes the electrical parameter of the channel by dynamically controlling the state of data input/output switches. By turning off switches for unselected memories, the effective capacitance of the channel is reduced, allowing standard driving forces to achieve good signal integrity without causing overshoot or undershoot phenomena that would result from excessively strong driving forces
3Reliability
If data input/output switches of unselected memories are turned off to reduce parasitic capacitance, then channel capacitance is reduced improving signal integrity, but device complexity increases due to switch control circuitry
Solution Approach 1:
The control circuit for the data input/output switches is integrated into the existing memory device architecture, allowing the same control logic to serve multiple functions: managing switch states for parasitic capacitance reduction, coordinating with memory selection signals, and maintaining compatibility with standard memory operations. This multi-functional approach reduces the net increase in device complexity while achieving signal integrity improvements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces parasitic capacitance by selectively turning on/off data input/output switches of unselected memories, maintaining channel capacitance at a reference value, which enhances signal integrity and reliability of data storage operations.
Implementation Method 1
parasitic capacitance of unselected nonvolatile memories when performing a read, write or copy-back operation on a selected device
Implementation Method 2
The switch may include a transmission gate including at least one NMOS transistor and at least one PMOS transistor connected in parallel and driven by the switching voltage
Data Source
AI summary
A nonvolatile memory includes a memory cell array including a plurality of memory cells, a pad configured to be connected to a data input/output line, and an input/output circuit configured to receive data to be programmed in the memory cell array and to transmit data read from the memory cell array. The nonvolatile memory further includes a switch configured to couple and decouple the pad and the input/output circuit responsive to a switch control signal and a control circuit configured to generate the switch control signal responsive to a chip enable signal. Data storage devices and methods using such nonvolatile memories are also described.