Non-Volatile Memory Word Line Programming Compensation
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Solution Overview
Problem
In non-volatile semiconductor memory, variations in time constants along a word line cause inefficiencies in programming efficacy, leading to differences in programmed threshold values between memory elements close to and far from the row decoder, which degrade performance and require additional programming pulses.
Innovation Solution
Adjusting bit line voltages across the memory plane based on distance from the word line voltage source to modify programming rates, thereby compensating for variations in programming efficacy, with different voltages applied to different halves of the memory plane to minimize programming pulse requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If fixed bit line voltages are used for all memory cells, then the memory structure is simple, but programming efficacy varies significantly along the word line causing performance degradation
Solution Approach 1:
The patent applies local quality by dividing the memory array into multiple regions along the word line direction and applying different bit line voltages to each region. Memory cells closer to the row decoder receive different voltage levels compared to cells farther away, compensating for the varying programming efficacy caused by RC delays along the word line. This spatial differentiation of voltage levels ensures uniform programming effectiveness across all cells despite structural simplicity.
2Manufacturing precision
If additional programming pulses are applied to compensate for variations, then programming precision is improved, but programming time increases
Solution Approach 1:
The patent implements preliminary action by pre-calculating and pre-applying different bit line voltages to different regions of the memory array before the actual programming operation. This anticipatory voltage adjustment compensates for the RC delays that will occur during programming, ensuring that all memory cells receive the appropriate voltage level from the start. This eliminates the need for additional programming pulses to compensate for variations, thereby maintaining programming precision while avoiding time penalties.
3Reliability
If bit line voltages are adjusted across the memory plane, then programming efficacy uniformity is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the memory array into distinct regions based on their distance from the row decoder along the word line. Each region is assigned a specific bit line voltage level, creating a segmented voltage control scheme. This segmentation approach manages complexity by organizing the voltage control into discrete, manageable zones rather than requiring continuous or uniform voltage adjustment across the entire array, thereby achieving uniform programming efficacy while keeping the control mechanism practical.
Data Source
AI summary
Variation in programming efficacy due to variation in time constants along a word line that spans across a memory plane is compensated by adjusting the bit line voltages across the plane to modify the programming rates. In this way, the variation in programming efficacy is substantially reduced during programming of a group of memory cells coupled to the word line. This will allow uniform optimization of programming across the group of memory cells and reduce the number of programming pulses required to program the group of memory cells, thereby improving performance. In one embodiment, during programming, the bit lines in a first half of the memory plane closer to a source of word line voltage is set to a first voltage by a first voltage shifter and the bit lines in a second half of the memory plane further from the source of word line voltage is set to a second voltage by a second voltage shifter.