Word Line Test Circuit Defect Detection

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Solution Overview

Problem

Storage devices face performance deterioration due to undetected defects in word lines, which can lead to data loss and reduced operational efficiency.

Innovation Solution

A word line test circuit is implemented to detect defects by generating a test voltage, reflecting the current of a target word line, and comparing it with a reference voltage, using a comparison signal and reference clock counts to determine if a word line is defective.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a word line test circuit is implemented to detect defects, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improvedefect detection capabilityVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The test circuit uses universal components (comparator, counter, clock generator) that can detect defects across multiple word lines, making the testing mechanism applicable to the entire memory array rather than requiring dedicated test circuits for each word line

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent introduces an intermediary capacitive element that stores the current from the target word line and converts it into a voltage signal for comparison, enabling indirect measurement of word line characteristics without direct complex measurement circuits

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If test voltage is applied to generate current for defect detection, then measurement precision is improved, but use of energy increases

Engineering Contradiction:
Improveword line defect detection accuracyVSAvoidtest operation power consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The test circuit operates periodically by applying test voltage only when needed for defect detection, rather than continuously monitoring word lines, thereby reducing overall energy consumption while maintaining detection precision when required

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The test circuit adjusts the test voltage parameter dynamically - applying voltage only to selected target word lines under test rather than to all word lines simultaneously, optimizing energy usage based on testing requirements

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively prevents performance deterioration by accurately detecting defective word lines, ensuring reliable data storage and maintaining operational efficiency.

Implementation Method 1

charging a capacitive charger to a steady voltage level based on the current

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS11257559B1Test circuit, memory device, storage device, and method of operating the same
Publication Date: 2022.02.22 SK HYNIX INC
  • US11257559B1 patent drawing
  • US11257559B1 patent drawing
  • US11257559B1 patent drawing

AI summary

Provided herein may be a test circuit, a memory device, a storage device, and a method of operating the same. The word line test circuit may include an operation signal generator configured to generate a plurality of operation signals in response to a test command, a comparison result generator configured to, in response to the plurality of operation signals, generate a target voltage based on a test current, in which a current of a target word line varying with a test voltage is reflected, and to generate a comparison signal based on a result of a comparison between the target voltage and a reference voltage, and a word line defect detector configured to detect a defect in the target word line based on at least one reference count and a count of a reference clock, cycles of which are counted until a level of the comparison signal changes from a first level to a second level.