Non-volatile Memory Erase Control via GIDL Voltage Adjustment
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Solution Overview
Problem
Current memory devices face challenges in efficiently performing erase operations in 3D stacked memory devices, leading to potential over-erasure and degradation, particularly due to variations in erase rates among memory cells.
Innovation Solution
The implementation of a Gate Induced Drain Leakage (GIDL) erasing method, where an erase voltage and an erase control voltage are dynamically adjusted based on the presence of slow erase cells, ensuring optimal voltage differences to prevent over-erasure and maintain reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a uniform erase voltage is applied to all memory cells, then the erase operation is simple to implement, but fast-erasing memory cells are over-erased causing degradation
Solution Approach 1:
The patent applies different erase voltages to different subsets of memory cells based on their erase characteristics. Fast-erasing memory cells receive a first erase voltage while slow-erasing memory cells receive a second erase voltage, ensuring each subset is erased appropriately without over-erasure or under-erasure, thus preventing degradation while maintaining reliability.
2Productivity
If the erase voltage is increased to erase slow-erasing memory cells, then all memory cells can be erased, but fast-erasing memory cells are over-erased
Solution Approach 1:
The patent divides memory cells into subsets and applies different erase voltages to each subset. Slow-erasing memory cells receive a higher second erase voltage to ensure complete erasure, while fast-erasing memory cells receive a lower first erase voltage to prevent over-erasure, thus achieving both erase completeness and reliability.
Solution Approach 2:
The patent dynamically adjusts the erase voltage based on the erase characteristics of different memory cell subsets. By controlling select gate transistors to apply appropriate voltages to different subsets, the system adapts the erase operation to the actual state of memory cells, preventing over-erasure while ensuring complete erasure of slow-erasing cells.
3Speed
If the erase operation is performed on all memory cells simultaneously, then the erase process is fast, but variations in erase rates cause some cells to be over-erased
Solution Approach 1:
The patent segments memory cells into different subsets based on their erase characteristics and erases each subset with appropriately controlled voltages. This segmentation allows the erase operation to proceed efficiently while maintaining uniformity, as each subset receives the specific voltage needed for its erase rate, preventing over-erasure of fast-erasing cells.
Solution Approach 2:
The patent applies different erase voltages to different subsets of memory cells based on their local erase characteristics. Fast-erasing subsets receive lower voltages while slow-erasing subsets receive higher voltages, ensuring uniform erase quality across all cells while maintaining overall erase speed through parallel processing of subsets.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the erase operation efficiency by adapting to the characteristics of individual memory cells, reducing the risk of over-erasure and improving the overall reliability and capacity of 3D stacked memory devices.
Implementation Method 1
whether there are slow erase cells may be determined, and an erase voltage and an erase control voltage may be adjusted based on the determination result. For example, when it is determined that there are slow erase cells, a difference between a GIDL control voltage and a drain voltage may be increased.
Data Source
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AI summary
Provided are a non-volatile memory device and an erasing method thereof. The erasing method of the non-volatile memory device including a plurality of cell strings in which memory cells and selection transistors are connected, includes: performing a first erase operation based on an erase voltage provided to a first electrode of at least one of the selection transistors and an erase control voltage provided to a second electrode of the at least one of the selection transistors; determining whether there are slow erase cells by performing a multiple erase verify operation based on first and second verify voltages, the second verify voltage being higher than the first verify voltage; adjusting, when there are slow erase cells, the erase control voltage such that a voltage difference between the erase voltage and the erase control voltage increases; and performing a second erase operation based on the adjusted erase control voltage.