Nonvolatile Memory Erase Method Using String Select Line Precharge
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Solution Overview
Problem
As the capacity of nonvolatile memory devices increases by storing more bits in each memory cell, the operation speed of these devices is reduced due to the need for additional programming and reading operations, which affects the overall performance.
Innovation Solution
The proposed erase method involves applying a precharge voltage to a string select line, floating it, and then applying an erase voltage to the substrate, while also managing the voltage levels of string select lines and word lines to minimize hole trapping and reduce threshold voltage reduction in string select transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of bits stored in memory cell increases, then storage capacity increases, but operation speed reduces
Solution Approach 1:
The memory device is divided into multiple stacks, each containing multiple cell strings with memory cells arranged in three-dimensional space. This segmentation allows parallel access to multiple memory cells, enabling higher storage capacity without proportionally increasing operation time. The patent implements this by creating vertical stacks of memory cells that can be independently accessed through word lines and bit lines.
Solution Approach 2:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional stacking, where memory cells are arranged vertically in multiple layers. This dimensional change allows significantly more memory cells to be packed into the same footprint area, increasing storage capacity while maintaining fast access times through selective word line activation.
2Quantity of substance
If additional programming and reading operations are needed, then storage capacity increases, but operation speed reduces
Solution Approach 1:
The patent applies preliminary actions during the erase operation by pre-charging string select lines and applying voltages to word lines before the actual erase process. This preliminary voltage application ensures that when the erase operation commences, the electrical conditions are already optimized, reducing the total time required for the erase operation and improving overall operation speed.
Solution Approach 2:
The patent employs precise control of voltage parameters during erase operations, including applying different voltages to different word lines and string select lines at different times. By dynamically adjusting these voltage parameters, the patent achieves efficient erasure of multi-bit memory cells without requiring excessive operation time, thus maintaining high operation speed while supporting increased storage capacity.
3Reliability
If erase voltage is applied to substrate, then memory cells are erased, but holes may be trapped reducing transistor performance
Solution Approach 1:
The patent applies preliminary anti-action by pre-charging string select lines with a first voltage before applying the erase voltage to the substrate. This preliminary voltage application creates an opposing electrical field that counteracts the tendency of holes to be trapped in the string select transistors during the erase operation. By establishing this counter-field in advance, the patent prevents threshold voltage degradation and maintains transistor performance.
Solution Approach 2:
The patent uses word lines and string select lines as intermediary elements to control the erase process. By applying voltages to these intermediary conductors in a specific sequence and pattern, the patent mediates the interaction between the erase voltage and the memory cells, ensuring that holes are directed away from critical transistor regions while still achieving complete erasure of the memory cells.
Data Source
AI summary
An erase method of a nonvolatile memory device including a plurality of cell strings on a substrate is provided. Each string includes a plurality of memory cells stacked in a direction perpendicular to the substrate, a ground select transistor between the memory cells and the substrate, and string select transistors between the memory cells and a bit line. The erase method includes applying a precharge voltage during a first time to a first string select line, floating the first string select line during a second time after the first time, and applying an erase voltage to the substrate after the first time. The first string select line is connected to the string select transistors at a first height in the cell strings of a same row.