Vertical NAND String Select Gate for Density and Reliability
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Solution Overview
Problem
Current NAND flash memory devices face challenges in increasing memory density while maintaining reliability, as reducing feature size increases the risk of tunnel dielectric failure and charge leakage, and stacking semiconductor layers becomes costly and problematic.
Innovation Solution
The implementation of a vertical structure for NAND memory cells, where strings of memory cells are formed in a folded arrangement, with a self-aligned string select gate between each end, allowing for a reduced effective cell size and improved memory density without the need for thin tunnel dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature size is reduced to increase memory density, then memory density is improved, but the risk of tunnel dielectric failure and charge leakage increases
Solution Approach 1:
The patent transitions from planar memory cell arrangement to a three-dimensional vertical structure where memory cells are stacked above semiconductor pillars. This dimensional change allows memory density to increase without further reducing lateral feature sizes, thereby maintaining tunnel dielectric thickness and reliability while achieving higher storage capacity.
2Quantity of substance
If multiple layers of memory arrays are stacked to increase density, then memory density is improved, but fabrication complexity and cost increase
Solution Approach 1:
The memory structure is segmented into multiple vertical strings of memory cells formed around separate semiconductor pillars. Each pillar serves as an independent channel region, allowing the memory array to be divided into discrete, manageable units that can be fabricated using standardized processes, thereby reducing overall fabrication complexity while maintaining high density.
Solution Approach 2:
Instead of stacking memory arrays in the lateral plane, the patent utilizes the vertical dimension by forming memory cells around vertical semiconductor pillars. This approach increases density through vertical stacking rather than lateral expansion, simplifying the fabrication process as each pillar can be independently formed using conventional semiconductor manufacturing techniques.
3Quantity of substance
If feature size is reduced to increase memory density, then memory density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent achieves higher memory density by extending the memory structure vertically around pillars rather than reducing lateral feature sizes. This allows the tunnel dielectric layer to maintain its original thickness with standard manufacturing precision, as the density increase comes from the vertical dimension where precision requirements are less stringent.
Data Source
AI summary
Strings of memory cells having a string select gate configured to selectively couple ends of a string to a data line and a source line concurrently, memory devices incorporating such strings and methods for accessing and forming such strings are provided. For example, non-volatile memory devices are disclosed that utilize vertical structure NAND strings of serially-connected non-volatile memory cells. One such string including two or more serially-connected non-volatile memory cells where each end of the string shares a string select gate with the other end of the string is disclosed.