NAND Flash Memory Test Latch Circuit for Reduced Testing Time
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Solution Overview
Problem
Conventional NAND-type flash memory testing methods are time-consuming due to the need to input data patterns for each page, limited pin usage in testers, and potential interference between bit lines, leading to increased test time and complexity.
Innovation Solution
A NAND-type flash memory device with a memory cell array, bit lines, sense amplifiers, data latch circuits, and a test latch circuit, along with a data switching circuit that controls data distribution among latch circuits, allowing for simultaneous data latching and reducing the need for repeated data input across multiple latch circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data patterns are input for each page during testing, then testing coverage is improved, but test time is lengthened
Solution Approach 1:
The test latch circuit pre-latches test data patterns before actual testing begins. This preliminary action allows multiple data patterns to be prepared in advance, eliminating the need to input data repeatedly for each page during testing, thus reducing test time while maintaining comprehensive coverage
Solution Approach 2:
The test latch circuit creates copies of test data patterns that can be distributed to multiple data latch circuits simultaneously. This copying mechanism enables the same test patterns to be applied across different pages without repeated external input, solving the time-consuming data input problem
2Productivity
If the number of pins used for one chip is reduced in special mode, then the number of chips that can be measured simultaneously is increased, but the number of clocks needed to input commands and test data patterns is increased
Solution Approach 1:
The test latch circuit merges multiple data pattern inputs into a single external input interface. By consolidating the data input function, the system can supply test patterns to multiple chips simultaneously through shared pins, increasing productivity without proportionally increasing pin requirements
Solution Approach 2:
The test latch circuit acts as an intermediary between the external tester and the data latch circuits. It receives test data externally and distributes it to multiple internal data latch circuits, reducing the number of external pins needed while maintaining the ability to test multiple chips in parallel
3Reliability
If data patterns are supplied corresponding to bit line potential combinations, then interference between bit lines is addressed, but the kinds of data patterns increase and test time is lengthened
Solution Approach 1:
The test latch circuit pre-latches various data patterns that correspond to different bit line potential combinations before testing begins. This preliminary preparation allows all necessary test patterns to be ready in advance, enabling comprehensive interference detection without the time penalty of generating patterns during testing
Data Source
AI summary
A NAND-type flash memory has a memory cell array having NAND cells, each having memory cells capable of being rewritten electrically, a drain of one memory cell and a source of the other memory cell neighboring in a first direction being connected to each other, each of the NAND cells being arranged in a second direction, a plurality of bit lines, each being provided for each of the NAND cells, a plurality of sense amplifiers, each being provided for each of the bit lines, a plurality of data latch circuits, each being provided for each of the sense amplifiers, each of the data latch circuits temporarily holding data sent to and received from the corresponding sense amplifier, at least one test latch circuit which temporarily holds test data supplied from outside, and a data switching circuit which performs control for supplying at least two among the data latch circuits with data held in the test latch circuit.