Trimming 3D NAND Control Transistors for Leakage and Speed
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Solution Overview
Problem
In 3D NAND Flash memory arrays, the control transistors' threshold voltages (Vt) are difficult to manage effectively, leading to issues such as slow programming speed, poor programming inhibition, read failures, and unintended leakage, which affect the overall performance and reliability of the memory array.
Innovation Solution
A method for trimming control transistors, including string select, upper ground select, and ground select transistors, using incremental step pulse programming and self-boosting techniques to adjust their threshold voltages, ensuring precise control and minimizing interference with unselected transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If control transistor threshold voltages are adjusted to improve programming speed, then programming speed is improved, but leakage control and read reliability deteriorate
Solution Approach 1:
The patent applies parameter changes by adjusting the threshold voltage (Vt) of control transistors through trimming processes. Different Vt values are assigned to different control transistor types (string select, upper ground select, ground select) to optimize their respective functions. This parameter optimization resolves the contradiction by finding the optimal Vt range that balances programming speed with leakage control and read reliability.
2Loss of energy
If control transistor threshold voltages are increased to reduce leakage, then leakage is reduced, but programming speed and programming inhibition deteriorate
Solution Approach 1:
The patent applies local quality by assigning different threshold voltage characteristics to different control transistor locations and functions. String select transistors have one Vt optimization for fast selection, while ground select transistors have different Vt optimization for leakage control. This localized optimization resolves the contradiction by allowing different parts of the system to have different Vt characteristics suited to their specific functions.
3Ease of manufacture
If uniform threshold voltage trimming is applied to all control transistors, then manufacturing simplicity is maintained, but performance optimization and interference control deteriorate
Solution Approach 1:
The patent applies segmentation by dividing the control transistor population into distinct groups (string select, upper ground select, ground select) and applying different trimming strategies to each group. This segmentation allows each transistor type to be optimized for its specific function while maintaining a systematic trimming approach that is manufacturable.
4Productivity
If aggressive trimming is applied to improve performance, then performance is improved, but interference with unselected transistors and unintended leakage increase
Solution Approach 1:
The patent applies preliminary anti-action by carefully controlling the trimming process to prevent unintended side effects before they occur. The trimming methodology includes monitoring and control mechanisms that prevent over-trimming and interference with unselected transistors, thus avoiding the generation of harmful leakage effects while still achieving performance improvement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The trimming process results in more predictable and controlled Vt distributions for control transistors, reducing leakage and improving the performance of read, program, and erase operations, enhancing the reliability and efficiency of the memory array.
Implementation Method 1
A method for trimming control transistors, including string select, upper ground select, and ground select transistors, using incremental step pulse programming
Implementation Method 2
A method for trimming control transistors, including string select, upper ground select, and ground select transistors, using incremental step pulse programming and self-boosting techniques
Data Source
AI summary
Control transistors and memory cells within 3D NAND Flash memory arrays may both be created using the same technology, such as charge trapping structures, to simplify the fabrication process. However, the resulting control transistors may initially have higher variability in threshold voltages, when compared to traditional gate-oxide-based control transistors. Provided are exemplary techniques to trim control transistors to provide increased reliability and performance during array operation.