Flash Memory Trench Isolation By-Product Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing flash memory device manufacturing processes, such as the self-aligned source (SAS) process, result in increased contact resistance and surface damage due to high-energy impurity ion implantation, leading to degraded programming characteristics and reading speed, especially when combined with shallow trench isolation (STI) processes.
Innovation Solution
A flash memory device and manufacturing method involving trench lines on a semiconductor substrate with a common source region formed by impurity ion implantation along the word line direction, accompanied by a uniform by-product layer on the common source region, using a plasma etching process to minimize surface resistance and prevent substrate damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If high-energy impurity ion implantation is used to form the common source line through SAS process, then the junction depth is achieved, but the surface resistance increases and contact resistance increases
Solution Approach 1:
A protective film is formed on the semiconductor substrate before ion implantation to prevent surface damage. This preliminary protective action allows high-energy ions to reach the desired junction depth without creating surface defects that would increase contact resistance.
Solution Approach 2:
The patent introduces an intermediate protective film layer between the ion beam and the semiconductor substrate surface. This intermediary layer absorbs the harmful impact of high-energy ions while still allowing them to penetrate to the required depth, thereby mediating between the need for deep junctions and the need to maintain low surface resistance.
2Area of moving object
If SAS process and STI process are simultaneously applied to shrink cell size, then cell dimension is reduced, but source resistance increases remarkably
Solution Approach 1:
The protective film is applied selectively to regions where ion implantation occurs, providing localized protection exactly where high-energy ions will impact. This local quality approach ensures that the protective function is concentrated where needed to prevent surface damage without interfering with the overall cell shrinkage achieved by SAS and STI processes.
3Area of moving object
If trench depth is increased to maintain high voltage characteristics in smaller cells, then cell size is reduced, but the length of common source line increases, adversely affecting source resistance
Solution Approach 1:
The patent converts the potentially harmful effect of increased common source line length into a beneficial outcome by using the protective film to prevent surface damage along the entire line. This allows the longer line to maintain low resistance despite its increased length, effectively turning the disadvantage of scaling into an opportunity to demonstrate the protective film's effectiveness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces contact resistance and surface damage, maintaining the vertical trench profile and improving the reliability and characteristics of the semiconductor device by uniformly depositing by-products during isolation layer removal and ion implantation.
Implementation Method 1
Impurity ions such as arsenic (As) are implanted with high energy so as to form a junction having a predetermined depth on the common source line formed through the SAS process
Implementation Method 2
A flash memory device and manufacturing method involving trench lines on a semiconductor substrate with a common source region formed by impurity ion implantation along the word line direction, accompanied by a uniform by-product layer on the common source region, using a plasma etching process to minimize surface resistance and prevent substrate damage
Data Source
AI summary
Disclosed is a flash memory device. The flash memory device includes a plurality of trench lines in an isolation region of a semiconductor device, a common source region along a word line (WL) direction under a surface portion of the semiconductor substrate, a plurality of gate lines along a vertical direction of the trench line, a drain region on an opposite side of the gate line to the common source region, a drain contact over the drain region, and a uniform by-product layer on the common source region.