Flash Memory Trench Structure Blocks Secondary Electron Diffusion
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Solution Overview
Problem
As semiconductor devices, including flash memory devices, are scaled smaller, transient program disturb (TPD) becomes a significant challenge due to secondary electrons injected into adjacent memory cells during programming, affecting the memory window of dual bit devices.
Innovation Solution
The fabrication method involves forming a trench and impurity doped regions between gate stacks to block secondary electrons, using a multi-layer dielectric-charge trapping-dielectric stack and control gates, and implanting N-type impurities to create bitline regions that prevent electron diffusion between memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If dual bit memory devices are scaled smaller, then device density is improved, but transient program disturb increases
Solution Approach 1:
The patent introduces a trench structure that divides the substrate into separate regions between adjacent memory cells. This segmentation physically isolates the hot carrier generation region from adjacent cells, preventing secondary electron injection while maintaining high device density through compact layout.
Solution Approach 2:
The patent introduces a modified bitline structure with specific doping profiles that acts as an intermediary region between the control gate and charge trapping layer. This intermediary structure controls carrier acceleration and prevents harmful secondary electron generation while maintaining programming functionality.
2Ease of manufacture
If hot electron injection is used for programming, then memory cell programming is achieved, but secondary electrons are generated that affect adjacent cells
Solution Approach 1:
The patent modifies the bitline doping profile to intentionally create a controlled depletion region that captures and neutralizes secondary electrons before they can reach adjacent cells. The harmful secondary electrons are converted into a controlled phenomenon that no longer causes program disturb.
Solution Approach 2:
The patent pre-configures the bitline doping profile and trench structure before programming operations to prevent secondary electron generation and migration. The anti-action is built into the device structure itself, preventing the harmful effect before it can occur during normal programming operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces transient program disturb, allowing for reliable programming of dual bit memory devices while enabling scaling to smaller device dimensions without adverse effects on memory cell integrity.
Implementation Method 1
A MirrorBit cell effectively doubles the intrinsic density of a flash memory array by storing two physically distinct bits on opposite sides of a memory cell. Each bit within a cell can be programmed with a binary unit of data
Implementation Method 2
The voltage on the control gate 26 inverts a channel region 36 while the bias accelerates electrons from bitline 14 into the channel region 36 towards bitline 16
Implementation Method 3
the bias accelerates electrons from bitline 14 into the channel region 36 towards bitline 16. The 4.5 eV to 5 eV kinetic energy gain of the electrons is more than sufficient to surmount the 3.1 eV to 3.5 eV energy barrier
Implementation Method 4
hot holes generated during programming of first bit 28 of memory cell 32 have a secondary impact ionization below bitline 16. Secondary electrons resulting from the secondary impact ionization diffuse to the disturbed cell 34 below gate 26 where they are accelerated by the drain depletion region
Data Source
AI summary
Methods for fabricating flash memory devices are provided. In accordance with an exemplary embodiment of the invention, a method for fabricating a memory device comprises forming a first gate stack and a second gate stack overlying a substrate. A trench is etched into the substrate between the first gate stack and the second gate stack. A first impurity doped region is formed within the substrate underlying the trench.