Variable Bit Allocation in Flash Memory to Reduce Capacitive Coupling
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Solution Overview
Problem
Flash memory devices face challenges in efficiently managing and updating data due to fixed bit allocation per word line, leading to stress concentration and reduced lifespan, especially in high-density memory applications where capacitive coupling effects degrade performance.
Innovation Solution
A flash memory device that dynamically adjusts the number of bits stored per word line, allowing for variable bit allocation based on bit count information managed in flag cells, which is updated during erasing operations, thereby reducing capacitive coupling and distributing stress evenly across the memory cell array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If fixed bit allocation per word line is used, then device structure is simple, but stress concentration occurs and lifespan is reduced
Solution Approach 1:
The patent implements dynamic bit allocation where the number of bits per word line can be changed based on wear levels. The memory device transitions from a fixed allocation structure to a dynamic one, allowing redistribution of data across different word lines to balance stress and extend lifespan.
Solution Approach 2:
The invention changes the parameter of bit allocation from fixed to variable. By modifying the bit allocation parameters dynamically based on wear indicators, the system optimizes reliability without requiring complete device redesign.
2Quantity of substance
If high-density memory applications are used, then storage capacity increases, but capacitive coupling effects worsen and performance degrades
Solution Approach 1:
The patent segments the memory device into multiple planes, with each plane having independent bit allocation configurations. This segmentation isolates capacitive coupling effects within individual planes and prevents them from affecting the entire device, allowing high-density storage while managing interference.
Solution Approach 2:
Different word lines within the same plane can have different bit allocations tailored to local conditions. This local quality approach allows optimization of each region to minimize capacitive coupling effects while maintaining overall high storage capacity.
3Reliability
If variable bit allocation is implemented, then stress distribution improves and lifespan extends, but device complexity increases
Solution Approach 1:
The patent merges multiple bit allocation configurations into a single memory device with multiple planes. Each plane can operate with different bit allocations, combining the benefits of various configurations without requiring separate devices.
Solution Approach 2:
The memory device achieves multi-functionality by supporting variable bit allocations across different planes and word lines. A single device structure performs multiple functions with different storage densities and wear characteristics, reducing the need for additional components.
Data Source
AI summary
A non-volatile memory device includes an array of non-volatile memory cells configured to support single bit and multi-bit programming states. A control circuit is provided, which is configured to program a first page of non-volatile memory cells in the array as M-bit cells during a first programming operation and further configured to program the first page of non-volatile memory cells as N-bit cells during a second programming operation. The first and second programming operations are separated in time by at least one operation to erase the first page of non-volatile memory cells. M and N are unequal integers greater than zero.