Flash Memory Erase Voltage Ramping for Transistor Stress Reduction
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Solution Overview
Problem
Current flash memory erase procedures cause significant voltage stress on driving transistors in unselected blocks, particularly in high-density NAND flash devices, leading to reliability concerns.
Innovation Solution
A method of erasing flash memory cells involves raising the cell well voltage in selected and unselected blocks to an intermediate voltage before reaching the target erase voltage, reducing the electrical field stress on driving transistors by gradually ramping up and down the voltage, thereby protecting them from excessive stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the cell well voltage is raised directly to the target erase voltage (20V) during erasure, then the erasing efficiency is improved, but the electrical field stress on driving transistors of unselected blocks increases to about 6.7MV/cm, causing reliability concerns
Solution Approach 1:
The patent applies preliminary action by raising the cell well voltage to an intermediate level (5V-10V) before reaching the final target erase voltage (20V). This preliminary voltage ramp allows the system to prepare for the high-voltage erase operation while preventing excessive electrical field stress on the driving transistors of unselected blocks, thereby resolving the contradiction between erasing efficiency and transistor reliability
Solution Approach 2:
The patent implements periodic action through a multi-stage voltage ramping process with distinct time periods: a first time period for raising voltage to the intermediate level, a second time period for maintaining or further raising the voltage, and subsequent periods for completing the erase operation. This time-based segmentation allows controlled stress management while achieving effective erasure
2Reliability
If the cell well voltage is raised to an intermediate voltage before the target erase voltage, then the electrical field stress on driving transistors is reduced, but the erasing time is extended due to multiple voltage ramping stages
Solution Approach 1:
The patent applies partial action by using an intermediate voltage level (5V-10V) that is sufficient to protect driving transistors during the critical ramp-up phase, while still enabling the subsequent application of the full target erase voltage (20V) for effective data erasure. This partial voltage application at different time stages optimizes both transistor protection and erasure completeness without excessive time loss
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the electrical field stress on word line driving transistors, enhancing the reliability of high-density flash memory devices by minimizing voltage-induced damage and maintaining erasing efficiency.
Implementation Method 1
This large voltage difference forces the electrons stored in the floating gate to escape into the cell well
Data Source
AI summary
In a method of erasing flash memory cells, the flash memory cells organized in selectable memory blocks, the erasing step comprising applying an erase pulse voltage to a commonly biased cell well of at least one selected and at least one unselected memory blocks, the method comprising the steps of: raising the erase pulse voltage to a first intermediate voltage less than a target erase pulse voltage; maintaining the erase pulse voltage at the first intermediate voltage for a first period of time; after the first time period, raising the erase pulse voltage to the target erase pulse voltage; and maintaining the erase pulse voltage at the target erase pulse voltage during an erase operation.